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MC33FS6500NAE

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NXP Semicon Power Management Specialized - PMIC, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsmc33fs6500naefactory-2.0.0extractor-text

Verified MC33FS6500NAE

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 48 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: MC33FS6500NAE · LQFP-48(7x7) · 48 pins
  • ✓copper: 48 copper pads, none touching another net
  • ✓datasheet: all 48 pin names found in the 161-page datasheet
  • ✓distributor: lcsc C1575052, digikey 568-13809-ND, mouser 841-MC33FS6500NAE
  • ✓family: LQFP-48_7x7mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-0n_m2gzc/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): the datasheet dimensions give no height or body size to compare (datasheet p.141)
  • ✓pads: 48 pins = 48 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 48 pins agree
  • ✓visibility: public, source open
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Verified files✓ mc33fs6500nae.kicad_sym✓ mc33fs6500nae.kicad_mod✓ mc33fs6500nae.step
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docs Publish 0.1.0 · Ray 5d ago
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verification.json Verified: Published by the parts factory: tier mfr, 48 pins · Ray 5d ago

MC33FS6500NAE

NXP Semicon · Power Management Specialized - PMIC · LQFP-48(7x7)

MC33FS6500NAE from NXP Semicon, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VSUP1 power_in Power supply of the device; an external reverse battery protection diode in series is mandatory, with VSUP1/2/3 rated -1.0 to 40 V DC.
2 VSUP2 power_in Second power supply, protected by the external reverse battery diode used for VSUP1, and must be connected together with VSUP1 externally.
3 VSENSE input Battery voltage sense input, which must be connected before the reverse battery protection diode through a series resistor (VSENSE DC rating -14 to 40 V).
4 VSUP3 power_in Third power supply for the device, protected by the external reverse battery diode and connected between the diode and the input PI filter.
5 n.c. unconnected LIN and FS1B functions are not present in this variant, so this pin must be left open.
6 GND_COM power_in Dedicated ground for the physical layers.
7 CAN_5V power_out Output voltage for the embedded CAN FD interface, as printed in Figure 7 for this variant.
8 n.c. unconnected CANH function is not present in this variant and the pin is left open.
9 n.c. unconnected CANL function is not present in this variant and the pin is left open.
10 IO_4 bidirectional Digital input (load dump proof) with selectable edge or level wake-up, or output gate driver for a logic level low-side NMOS; requires an external series resistor per the maximum ratings (VIO_0,4 -0.3 to 40 V).
11 IO_5/VKAM bidirectional Digital input with wake-up capability, or analog supply output providing keep-alive memory supply in low-power mode (VKAM rated -0.3 to 8 V).
12 IO_0 input Analog or digital input (load dump proof) with selectable wake-up; the key-off signal on this pin moves the device to LPOFF-deep FS when low.
13 FCRBM input Feedback core resistor bridge monitoring input for the middle point of a redundant VCORE resistor bridge; if unused it must be connected directly to FB_CORE.
14 FS0B output First fail-safe output, active low and asserted at start-up and on fault, with an open-drain structure that needs an external pull-up to VDDIO or VSUP3.
15 DEBUG input Debug mode entry input; the voltage must be within the VDEBUG_IL and VDEBUG_IH range at start-up (DEBUG rated -0.3 to 40 V).
16 AGND power_in Analog ground connection.
17 MUX_OUT output Multiplexed analog output to be connected to an MCU ADC, with the selected parameter set through the SPI.
18 IO_2 input Digital input with selectable wake-up (logic level compatible) that can monitor FCCU error signals from the MCU for safety purposes.
19 IO_3 input Digital input with selectable wake-up (logic level compatible) that can monitor FCCU error signals from the MCU for safety purposes.
20 n.c. unconnected TXD function is not used in this variant and the pin is left open.
21 n.c. unconnected RXD function is not used in this variant and the pin is left open.
22 n.c. unconnected VPU_FS and TXDL/FS1B functions are not present in this variant and the pin is left open.
23 n.c. unconnected RXDL function is not used in this variant and the pin is left open.
24 RSTB output Reset output asserted low when the safety block reports a failure to reset the MCU, with an open-drain structure and an external pull-up to VDDIO.
25 MISO output SPI bus data output in secondary mode, with its output buffer supplied from VDDIO.
26 MOSI input SPI bus data input in secondary mode.
27 SCLK input SPI serial clock input.
28 NCS input SPI chip select input, active low.
29 INTB output Interrupt output that generates a low pulse on an interrupt condition, with configurable pulse duration and an internal pull-up to VDDIO.
30 VDDIO power_in Input voltage for the MISO output buffer, allowing voltage compatibility with MCU I/Os (VDDIO rated -0.3 to 8 V).
31 SELECT input Hardware selection pin for the VCCA and VAUX output voltages, set by an external resistor to ground or VPRE.
32 FB_CORE input VCORE voltage feedback input to the error amplifier (FB_CORE rated -0.3 to 2.5 V).
33 COMP_CORE output Compensation network output of the VCORE error amplifier; it is used for the FS6500 SMPS.
34 VCORE_SNS input VCORE input voltage sense (VCORE_SNS rated 0.0 to 8 V).
35 SW_CORE output VCORE output switching point for the FS6500 series (SW_CORE rated -1.0 to 8 V).
36 BOOT_CORE bidirectional Bootstrap capacitor connection for the VCORE internal NMOS gate drive (BOOT_CORE rated 0.0 to 15 V).
37 VPRE input VPRE input voltage sense (VPRE rated -0.3 to 8 V).
38 VAUX output VAUX output voltage, with the collector connection of the external PNP ballast transistor.
39 VAUX_B output VAUX regulator base connection to the external PNP ballast transistor.
40 VAUX_E output VAUX regulator emitter connection to the external PNP ballast transistor.
41 VCCA_E output VCCA regulator emitter connection to the external PNP ballast transistor.
42 VCCA_B output VCCA regulator base connection to the external PNP ballast transistor.
43 VCCA power_in VCCA output voltage, with the collector connection of the external PNP ballast transistor.
44 GATE_LS output Low-side MOSFET gate drive for the non-inverting buck-boost configuration; it is detected at start-up by a 300 µA pull-up.
45 DGND power_in Digital ground connection.
46 BOOT_PRE bidirectional Bootstrap capacitor connection for the VPRE internal NMOS gate drive (BOOT_PRE rated -1.0 to 50 V).
47 SW_PRE2 output Second pre-regulator output switching point (SW_PRE rated -1.0 to 40 V).
48 SW_PRE1 output First pre-regulator output switching point (SW_PRE rated -1.0 to 40 V).

Key specifications

Parameter Value
Manufacturer NXP Semicon
Package LQFP-48(7x7)
Category Power Management ICs
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power supply current in normal mode ISUP123 15 mA 17
Power supply current for VSUP3 in normal mode ISUP3 3.5 5 mA 17
Power supply current in LPOFF ISUP_LPOFF1 32 µA VSUP = 14 V at TA = 25 °C 17
Power supply current in LPOFF ISUP_LPOFF2 42 60 µA VSUP = 18 V at TA = 80 °C 17
Power supply undervoltage warning VSNS_UV 7 8 9 V 17
Power supply undervoltage lockout (power up) VSUP_UV_7 7 8 V 17
Power supply undervoltage lockout (power up) VSUP_UV_5 5.6 V 17
Power supply undervoltage lockout (falling, boost configuration) VSUP_UV_L 2.7 V 17
VPRE output voltage, buck mode VPRE 6.25 6.75 V Buck mode (VSUP > VSUP_UV_7) 17
VPRE output voltage, boost mode VPRE 6 7 V Boost mode (VSUP ≥ 2.7 V) 17
VPRE maximum output current capability IPRE 2 A Buck or boost with VSUP > VSUP_UV_7 17
SW_PRE output current limitation in buck-boost mode IPRE_LIM1 3.5 A VSUP ≤ 28 V 17
SW_PRE output current limitation in buck mode IPRE_LIM2 2.5 A VSUP ≤ 28 V 17
SW_PRE overcurrent detection threshold in buck mode IPRE_OC 4.5 A VSUP ≤ 28 V 17
VPRE undervoltage detection threshold (falling) VPRE_UV 5.5 6 V 17
VPRE shut-off threshold (falling) VPRE_UV_4P3 4.1 4.5 V buck and buck/boost 17
VPRE pass transistor on resistance RDSON_PRE 200 mΩ VSUP ≤ 28 V 18
VPRE thermal shutdown threshold TSD_PRE 160 °C 18
VCORE feedback input voltage VCORE_FB 0.784 0.8 0.816 V 18
VCORE internal pull-down current IPD_CORE 5 12 25 mA active when VCORE is enabled 18
VCORE output current capability in normal mode ICORE 0.8 A FS650x 18
VCORE output current limitation ICORE_LIM 1 2 A FS650x 18
VCORE pass transistor on resistance RDSON_CORE 200 mΩ 18
VCORE transient load regulation, 1.2 V range FS65_LORVCORE_1.2 -60 60 mV COUT_VCORE = 40 µF, ICORE = 10 mA to 2.2 A, dICORE/dt ≤ 2.0 A/µs 18
VCORE transient load regulation, 3.3 V range FS65_LORVCORE_3.3 -100 100 mV COUT_VCORE = 40 µF, ICORE = 10 mA to 1.5 A, dICORE/dt ≤ 2.0 A/µs 18
VCORE transient load regulation, 5.0 V range FS65_LORVCORE_5 -150 150 mV COUT_VCORE = 20 µF, ICORE = 10 mA to 0.8 A, dICORE/dt ≤ 2.0 A/µs 18
VCORE thermal shutdown threshold TSD_CORE 160 °C 19
VCCA output voltage, 5.0 V configuration VCCA 4.95 5 5.05 V 5.0 V configuration with Internal ballast at 100 mA 19
VCCA output voltage, 3.3 V configuration VCCA 3.267 3.3 3.333 V 3.3 V configuration with Internal ballast at 100 mA 19
VCCA output current (int. MOSFET) ICCA_IN 100 mA 19
VCCA output current limitation (int. MOSFET) ICCA_LIM_INT 100 675 mA 19
VCCA internal pull-down resistor RPD_CCA 50 170 Ω active when VCCA is disabled 19
VAUX output voltage (5.0 V configuration) VAUX_5 4.85 5 5.15 V 19
VAUX output voltage (3.3 V configuration) VAUX_33 3.2 3.3 3.4 V 19
VAUX output current IAUX_OUT 400 mA 19
VAUX output current limitation IAUX_LIM 400 800 mA 20
VAUX internal pull-down resistor RPD_AUX 50 170 Ω active when VAUX is disabled 20
VKAM output voltage VKAM 3 3.5 4 V 20
VKAM output current IKAM_OUT 3 mA 20
VKAM output current limitation IKAM_LIM 4 10 mA 20
VPRE overvoltage detection threshold VPRE_OV 7.2 8 V 20
VCORE FB undervoltage detection threshold VCORE_FB_UV 0.67 0.773 V 20
VCORE FB overvoltage detection threshold VCORE_FB_OV 0.84 0.905 V 21
VCCA undervoltage detection threshold (5.0 V configuration) VCCA_UV_5 4.5 4.75 V 21
VCCA overvoltage detection threshold (5.0 V configuration) VCCA_OV_5 5.25 5.5 V 21
Reset low output level VRSTB_OL 0.5 V I_RSTB = 2.0 mA 21
FS0B low output level VFS0B_OL 0.5 V I_FS0B = 2.0 mA 21
SPI operation frequency fSPI 0.5 8 MHz 50 % DC 26
Reset delay time (after a power-on reset or from LPOFF) tRSTB_POR 12.5 16.5 24.3 ms 26
Minimum capacitor on VSUP CSUP 47 µF 27
VPRE switching frequency fSW_PRE 412 437.5 463 kHz 27
VCORE switching frequency fSW_CORE 2.2 2.34 2.48 MHz 27
Ambient temperature TA -40 125 °C 16
Junction temperature TJ -40 150 °C 16
Storage temperature TSTG -55 150 °C 16
Thermal resistance junction to ambient RθJA 30 °C/W Per JEDEC JESD51-6 with the board (JESD51-7) horizontal 16
Thermal resistance junction to case top RθJCTOP 23.8 °C/W cold plate method (MIL SPEC - 883 Method 1012.1) 16
Thermal resistance junction to case bottom RθJCBOTTOM 0.9 °C/W based on simulation without any interface resistance 16

CAD (KiCad official)

  • Symbol: MC33FS6500NAE
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: mc33fs6500nae-etched.step / mc33fs6500nae-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc33fs6500nae.step / mc33fs6500nae.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: NXP Semicon datasheet (161 pp, sha256 39f5c318b818b984, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF