component
MC14076BDR2G
Public Made by Adomby adom
onsemi Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
MC14076BDR2G
onsemi · Flip Flops · SOIC-16
MC14076BDR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUTPUT DISABLE A | input | OR-gated output-disable input; when either output disable A or B is high, the Q outputs go to the high-impedance state without affecting flip-flop sequencing. |
| 2 | OUTPUT DISABLE B | input | OR-gated output-disable input; when either output disable A or B is high, the Q outputs go to the high-impedance state without affecting flip-flop sequencing. |
| 3 | Q0 | tri_state | Three-state output of flip-flop 0, which goes high-impedance when output disable A or B is high; unused outputs must be left open. |
| 4 | Q1 | tri_state | Three-state output of flip-flop 1, which goes high-impedance when output disable A or B is high; unused outputs must be left open. |
| 5 | Q2 | tri_state | Three-state output of flip-flop 2, which goes high-impedance when output disable A or B is high; unused outputs must be left open. |
| 6 | Q3 | tri_state | Three-state output of flip-flop 3, which goes high-impedance when output disable A or B is high; unused outputs must be left open. |
| 7 | CLOCK | input | Common clock that synchronously loads the four D-type flip-flops; the clock input is fully independent of the reset and disable inputs. |
| 8 | VSS | power_in | Negative supply and reference for all voltages; inputs and outputs must stay within VSS ≤ (Vin or Vout) ≤ VDD. |
| 9 | DATA DISABLE B | input | OR-gated data-disable input; when either data disable A or B is high, the Q outputs are fed back to the D inputs so the registers hold state while the clock continues. |
| 10 | DATA DISABLE A | input | OR-gated data-disable input; when either data disable A or B is high, the Q outputs are fed back to the D inputs so the registers hold state while the clock continues. |
| 11 | D3 | input | Parallel data input to flip-flop 3; unused inputs must be tied to VSS or VDD and must not be left floating. |
| 12 | D2 | input | Parallel data input to flip-flop 2; unused inputs must be tied to VSS or VDD and must not be left floating. |
| 13 | D1 | input | Parallel data input to flip-flop 1; unused inputs must be tied to VSS or VDD and must not be left floating. |
| 14 | D0 | input | Parallel data input to flip-flop 0; unused inputs must be tied to VSS or VDD and must not be left floating. |
| 15 | RESET | input | Asynchronous master reset; when high it clears all four flip-flops to 0 independent of the clock or disable inputs. |
| 16 | VDD | power_in | Positive supply, specified from 3.0 Vdc to 18 Vdc with absolute maximum DC supply of −0.5 to +18.0 V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage Range | VDD | -0.5 | 18 | V | Voltages referenced to VSS | 1 | |
| Input or Output Voltage Range (DC or Transient) | Vin, Vout | -0.5 | V | DC or transient; upper limit printed as VDD + 0.5 | 1 | ||
| Input or Output Current (DC or Transient) per Pin | Iin, Iout | -10 | 10 | mA | DC or transient, per pin; printed as ±10 mA | 1 | |
| Power Dissipation, per Package | PD | 500 | mW | Per package (Note 1) | 1 | ||
| Ambient Temperature Range | TA | -55 | 125 | °C | 1 | ||
| Storage Temperature Range | Tstg | -65 | 150 | °C | 1 | ||
| Lead Temperature | TL | 260 | °C | 8-second soldering | 1 | ||
| Supply Voltage Range | VDD | 3 | 18 | Vdc | Supply voltage range as listed in Features | 1 | |
| Output Voltage '0' Level | VOL | 0 | 0.05 | Vdc | VDD 5.0 Vdc; Vin = VDD or 0; 25C | 3 | |
| Output Voltage '1' Level | VOH | 4.95 | 5 | Vdc | VDD 5.0 Vdc; Vin = 0 or VDD; 25C | 3 | |
| Output Voltage '1' Level | VOH | 9.95 | 10 | Vdc | VDD 10 Vdc; Vin = 0 or VDD; 25C | 3 | |
| Output Voltage '1' Level | VOH | 14.95 | 15 | Vdc | VDD 15 Vdc; Vin = 0 or VDD; 25C | 3 | |
| Input Voltage '0' Level | VIL | 2.25 | 1.5 | Vdc | VDD 5.0 Vdc; VO = 4.5 or 0.5 Vdc; 25C | 3 | |
| Input Voltage '0' Level | VIL | 4.5 | 3 | Vdc | VDD 10 Vdc; VO = 9.0 or 1.0 Vdc; 25C | 3 | |
| Input Voltage '0' Level | VIL | 6.75 | 4 | Vdc | VDD 15 Vdc; VO = 13.5 or 1.5 Vdc; 25C | 3 | |
| Input Voltage '1' Level | VIH | 3.5 | 2.75 | Vdc | VDD 5.0 Vdc; VO = 0.5 or 4.5 Vdc; 25C | 3 | |
| Input Voltage '1' Level | VIH | 7 | 5.5 | Vdc | VDD 10 Vdc; VO = 1.0 or 9.0 Vdc; 25C | 3 | |
| Input Voltage '1' Level | VIH | 11 | 8.25 | Vdc | VDD 15 Vdc; VO = 1.5 or 13.5 Vdc; 25C | 3 | |
| Output Drive Current, Source | IOH | -2.4 | -4.2 | mAdc | VDD 5.0 Vdc; VOH = 2.5 Vdc; 25C | 3 | |
| Output Drive Current, Source | IOH | -0.51 | -0.88 | mAdc | VDD 5.0 Vdc; VOH = 4.6 Vdc; 25C | 3 | |
| Output Drive Current, Source | IOH | -1.3 | -2.25 | mAdc | VDD 10 Vdc; VOH = 9.5 Vdc; 25C | 3 | |
| Output Drive Current, Source | IOH | -3.4 | -8.8 | mAdc | VDD 15 Vdc; VOH = 13.5 Vdc; 25C | 3 | |
| Output Drive Current, Sink | IOL | 0.51 | 0.88 | mAdc | VDD 5.0 Vdc; VOL = 0.4 Vdc; 25C | 3 | |
| Output Drive Current, Sink | IOL | 1.3 | 2.25 | mAdc | VDD 10 Vdc; VOL = 0.5 Vdc; 25C | 3 | |
| Output Drive Current, Sink | IOL | 3.4 | 8.8 | mAdc | VDD 15 Vdc; VOL = 1.5 Vdc; 25C | 3 | |
| Quiescent Current (Per Package) | IDD | 0.005 | 5 | Adc | VDD 5.0 Vdc; per package; 25C | 3 | |
| Quiescent Current (Per Package) | IDD | 0.01 | 10 | Adc | VDD 10 Vdc; per package; 25C | 3 | |
| Quiescent Current (Per Package) | IDD | 0.015 | 20 | Adc | VDD 15 Vdc; per package; 25C | 3 | |
| Input Capacitance | Cin | 5 | 7.5 | pF | Vin = 0; 25C | 3 | |
| Input Current | Iin | -0.1 | 1e-05 | 0.1 | Adc | VDD 15 Vdc; 25C; printed as ±0.1 | 3 |
| Three-State Leakage Current | ITL | -0.1 | 0.0001 | 0.1 | Adc | VDD 15 Vdc; 25C; printed as ±0.1 | 3 |
| Output Voltage '0' Level | VOL | 0.05 | Vdc | VDD 5.0 Vdc; Vin = VDD or 0; 125C | 3 | ||
| Output Voltage '1' Level | VOH | 4.95 | Vdc | VDD 5.0 Vdc; Vin = 0 or VDD; 125C | 3 | ||
| Output Voltage '1' Level | VOH | 9.95 | Vdc | VDD 10 Vdc; Vin = 0 or VDD; 125C | 3 | ||
| Output Voltage '1' Level | VOH | 14.95 | Vdc | VDD 15 Vdc; Vin = 0 or VDD; 125C | 3 | ||
| Input Voltage '0' Level | VIL | 1.5 | Vdc | VDD 5.0 Vdc; VO = 4.5 or 0.5 Vdc; 125C | 3 | ||
| Input Voltage '0' Level | VIL | 3 | Vdc | VDD 10 Vdc; VO = 9.0 or 1.0 Vdc; 125C | 3 | ||
| Input Voltage '0' Level | VIL | 4 | Vdc | VDD 15 Vdc; VO = 13.5 or 1.5 Vdc; 125C | 3 | ||
| Input Voltage '1' Level | VIH | 3.5 | Vdc | VDD 5.0 Vdc; VO = 0.5 or 4.5 Vdc; 125C | 3 | ||
| Input Voltage '1' Level | VIH | 7 | Vdc | VDD 10 Vdc; VO = 1.0 or 9.0 Vdc; 125C | 3 | ||
| Input Voltage '1' Level | VIH | 11 | Vdc | VDD 15 Vdc; VO = 1.5 or 13.5 Vdc; 125C | 3 | ||
| Quiescent Current (Per Package) | IDD | 150 | Adc | VDD 5.0 Vdc; per package; 125C | 3 | ||
| Quiescent Current (Per Package) | IDD | 300 | Adc | VDD 10 Vdc; per package; 125C | 3 | ||
| Quiescent Current (Per Package) | IDD | 600 | Adc | VDD 15 Vdc; per package; 125C | 3 | ||
| Output Drive Current, Source | IOH | -1.7 | mAdc | VDD 5.0 Vdc; VOH = 2.5 Vdc; 125C | 3 | ||
| Output Drive Current, Source | IOH | -0.36 | mAdc | VDD 5.0 Vdc; VOH = 4.6 Vdc; 125C | 3 | ||
| Output Drive Current, Source | IOH | -0.9 | mAdc | VDD 10 Vdc; VOH = 9.5 Vdc; 125C | 3 | ||
| Output Drive Current, Source | IOH | -2.4 | mAdc | VDD 15 Vdc; VOH = 13.5 Vdc; 125C | 3 | ||
| Output Drive Current, Sink | IOL | 0.36 | mAdc | VDD 5.0 Vdc; VOL = 0.4 Vdc; 125C | 3 | ||
| Output Drive Current, Sink | IOL | 0.9 | mAdc | VDD 10 Vdc; VOL = 0.5 Vdc; 125C | 3 | ||
| Output Drive Current, Sink | IOL | 2.4 | mAdc | VDD 15 Vdc; VOL = 1.5 Vdc; 125C | 3 | ||
| Input Current | Iin | -1 | 1 | Adc | VDD 15 Vdc; 125C; printed as ±1.0 | 3 | |
| Three-State Leakage Current | ITL | -3 | 3 | Adc | VDD 15 Vdc; 125C; printed as ±3.0 | 3 | |
| Quiescent Current (Per Package) | IDD | 5 | Adc | VDD 5.0 Vdc; per package; -55C | 3 | ||
| Quiescent Current (Per Package) | IDD | 10 | Adc | VDD 10 Vdc; per package; -55C | 3 | ||
| Quiescent Current (Per Package) | IDD | 20 | Adc | VDD 15 Vdc; per package; -55C | 3 |
CAD (KiCad official)
- Symbol:
MC14076BDR2G - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
mc14076bdr2g-etched.step/mc14076bdr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc14076bdr2g.step/mc14076bdr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (8 pp, sha256
df82d0401a9230af, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MC14076BDR2G
**onsemi** · Flip Flops · SOIC-16
MC14076BDR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUTPUT DISABLE A | input | OR-gated output-disable input; when either output disable A or B is high, the Q outputs go to the high-impedance state without affecting flip-flop sequencing. |
| 2 | OUTPUT DISABLE B | input | OR-gated output-disable input; when either output disable A or B is high, the Q outputs go to the high-impedance state without affecting flip-flop sequencing. |
| 3 | Q0 | tri_state | Three-state output of flip-flop 0, which goes high-impedance when output disable A or B is high; unused outputs must be left open. |
| 4 | Q1 | tri_state | Three-state output of flip-flop 1, which goes high-impedance when output disable A or B is high; unused outputs must be left open. |
| 5 | Q2 | tri_state | Three-state output of flip-flop 2, which goes high-impedance when output disable A or B is high; unused outputs must be left open. |
| 6 | Q3 | tri_state | Three-state output of flip-flop 3, which goes high-impedance when output disable A or B is high; unused outputs must be left open. |
| 7 | CLOCK | input | Common clock that synchronously loads the four D-type flip-flops; the clock input is fully independent of the reset and disable inputs. |
| 8 | VSS | power_in | Negative supply and reference for all voltages; inputs and outputs must stay within VSS ≤ (Vin or Vout) ≤ VDD. |
| 9 | DATA DISABLE B | input | OR-gated data-disable input; when either data disable A or B is high, the Q outputs are fed back to the D inputs so the registers hold state while the clock continues. |
| 10 | DATA DISABLE A | input | OR-gated data-disable input; when either data disable A or B is high, the Q outputs are fed back to the D inputs so the registers hold state while the clock continues. |
| 11 | D3 | input | Parallel data input to flip-flop 3; unused inputs must be tied to VSS or VDD and must not be left floating. |
| 12 | D2 | input | Parallel data input to flip-flop 2; unused inputs must be tied to VSS or VDD and must not be left floating. |
| 13 | D1 | input | Parallel data input to flip-flop 1; unused inputs must be tied to VSS or VDD and must not be left floating. |
| 14 | D0 | input | Parallel data input to flip-flop 0; unused inputs must be tied to VSS or VDD and must not be left floating. |
| 15 | RESET | input | Asynchronous master reset; when high it clears all four flip-flops to 0 independent of the clock or disable inputs. |
| 16 | VDD | power_in | Positive supply, specified from 3.0 Vdc to 18 Vdc with absolute maximum DC supply of −0.5 to +18.0 V referenced to VSS. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage Range | VDD | -0.5 | | 18 | V | Voltages referenced to VSS | 1 |
| Input or Output Voltage Range (DC or Transient) | Vin, Vout | -0.5 | | | V | DC or transient; upper limit printed as VDD + 0.5 | 1 |
| Input or Output Current (DC or Transient) per Pin | Iin, Iout | -10 | | 10 | mA | DC or transient, per pin; printed as ±10 mA | 1 |
| Power Dissipation, per Package | PD | | | 500 | mW | Per package (Note 1) | 1 |
| Ambient Temperature Range | TA | -55 | | 125 | °C | | 1 |
| Storage Temperature Range | Tstg | -65 | | 150 | °C | | 1 |
| Lead Temperature | TL | | | 260 | °C | 8-second soldering | 1 |
| Supply Voltage Range | VDD | 3 | | 18 | Vdc | Supply voltage range as listed in Features | 1 |
| Output Voltage '0' Level | VOL | | 0 | 0.05 | Vdc | VDD 5.0 Vdc; Vin = VDD or 0; 25C | 3 |
| Output Voltage '1' Level | VOH | 4.95 | 5 | | Vdc | VDD 5.0 Vdc; Vin = 0 or VDD; 25C | 3 |
| Output Voltage '1' Level | VOH | 9.95 | 10 | | Vdc | VDD 10 Vdc; Vin = 0 or VDD; 25C | 3 |
| Output Voltage '1' Level | VOH | 14.95 | 15 | | Vdc | VDD 15 Vdc; Vin = 0 or VDD; 25C | 3 |
| Input Voltage '0' Level | VIL | | 2.25 | 1.5 | Vdc | VDD 5.0 Vdc; VO = 4.5 or 0.5 Vdc; 25C | 3 |
| Input Voltage '0' Level | VIL | | 4.5 | 3 | Vdc | VDD 10 Vdc; VO = 9.0 or 1.0 Vdc; 25C | 3 |
| Input Voltage '0' Level | VIL | | 6.75 | 4 | Vdc | VDD 15 Vdc; VO = 13.5 or 1.5 Vdc; 25C | 3 |
| Input Voltage '1' Level | VIH | 3.5 | 2.75 | | Vdc | VDD 5.0 Vdc; VO = 0.5 or 4.5 Vdc; 25C | 3 |
| Input Voltage '1' Level | VIH | 7 | 5.5 | | Vdc | VDD 10 Vdc; VO = 1.0 or 9.0 Vdc; 25C | 3 |
| Input Voltage '1' Level | VIH | 11 | 8.25 | | Vdc | VDD 15 Vdc; VO = 1.5 or 13.5 Vdc; 25C | 3 |
| Output Drive Current, Source | IOH | -2.4 | -4.2 | | mAdc | VDD 5.0 Vdc; VOH = 2.5 Vdc; 25C | 3 |
| Output Drive Current, Source | IOH | -0.51 | -0.88 | | mAdc | VDD 5.0 Vdc; VOH = 4.6 Vdc; 25C | 3 |
| Output Drive Current, Source | IOH | -1.3 | -2.25 | | mAdc | VDD 10 Vdc; VOH = 9.5 Vdc; 25C | 3 |
| Output Drive Current, Source | IOH | -3.4 | -8.8 | | mAdc | VDD 15 Vdc; VOH = 13.5 Vdc; 25C | 3 |
| Output Drive Current, Sink | IOL | 0.51 | 0.88 | | mAdc | VDD 5.0 Vdc; VOL = 0.4 Vdc; 25C | 3 |
| Output Drive Current, Sink | IOL | 1.3 | 2.25 | | mAdc | VDD 10 Vdc; VOL = 0.5 Vdc; 25C | 3 |
| Output Drive Current, Sink | IOL | 3.4 | 8.8 | | mAdc | VDD 15 Vdc; VOL = 1.5 Vdc; 25C | 3 |
| Quiescent Current (Per Package) | IDD | | 0.005 | 5 | Adc | VDD 5.0 Vdc; per package; 25C | 3 |
| Quiescent Current (Per Package) | IDD | | 0.01 | 10 | Adc | VDD 10 Vdc; per package; 25C | 3 |
| Quiescent Current (Per Package) | IDD | | 0.015 | 20 | Adc | VDD 15 Vdc; per package; 25C | 3 |
| Input Capacitance | Cin | | 5 | 7.5 | pF | Vin = 0; 25C | 3 |
| Input Current | Iin | -0.1 | 1e-05 | 0.1 | Adc | VDD 15 Vdc; 25C; printed as ±0.1 | 3 |
| Three-State Leakage Current | ITL | -0.1 | 0.0001 | 0.1 | Adc | VDD 15 Vdc; 25C; printed as ±0.1 | 3 |
| Output Voltage '0' Level | VOL | | | 0.05 | Vdc | VDD 5.0 Vdc; Vin = VDD or 0; 125C | 3 |
| Output Voltage '1' Level | VOH | 4.95 | | | Vdc | VDD 5.0 Vdc; Vin = 0 or VDD; 125C | 3 |
| Output Voltage '1' Level | VOH | 9.95 | | | Vdc | VDD 10 Vdc; Vin = 0 or VDD; 125C | 3 |
| Output Voltage '1' Level | VOH | 14.95 | | | Vdc | VDD 15 Vdc; Vin = 0 or VDD; 125C | 3 |
| Input Voltage '0' Level | VIL | | | 1.5 | Vdc | VDD 5.0 Vdc; VO = 4.5 or 0.5 Vdc; 125C | 3 |
| Input Voltage '0' Level | VIL | | | 3 | Vdc | VDD 10 Vdc; VO = 9.0 or 1.0 Vdc; 125C | 3 |
| Input Voltage '0' Level | VIL | | | 4 | Vdc | VDD 15 Vdc; VO = 13.5 or 1.5 Vdc; 125C | 3 |
| Input Voltage '1' Level | VIH | 3.5 | | | Vdc | VDD 5.0 Vdc; VO = 0.5 or 4.5 Vdc; 125C | 3 |
| Input Voltage '1' Level | VIH | 7 | | | Vdc | VDD 10 Vdc; VO = 1.0 or 9.0 Vdc; 125C | 3 |
| Input Voltage '1' Level | VIH | 11 | | | Vdc | VDD 15 Vdc; VO = 1.5 or 13.5 Vdc; 125C | 3 |
| Quiescent Current (Per Package) | IDD | | | 150 | Adc | VDD 5.0 Vdc; per package; 125C | 3 |
| Quiescent Current (Per Package) | IDD | | | 300 | Adc | VDD 10 Vdc; per package; 125C | 3 |
| Quiescent Current (Per Package) | IDD | | | 600 | Adc | VDD 15 Vdc; per package; 125C | 3 |
| Output Drive Current, Source | IOH | -1.7 | | | mAdc | VDD 5.0 Vdc; VOH = 2.5 Vdc; 125C | 3 |
| Output Drive Current, Source | IOH | -0.36 | | | mAdc | VDD 5.0 Vdc; VOH = 4.6 Vdc; 125C | 3 |
| Output Drive Current, Source | IOH | -0.9 | | | mAdc | VDD 10 Vdc; VOH = 9.5 Vdc; 125C | 3 |
| Output Drive Current, Source | IOH | -2.4 | | | mAdc | VDD 15 Vdc; VOH = 13.5 Vdc; 125C | 3 |
| Output Drive Current, Sink | IOL | 0.36 | | | mAdc | VDD 5.0 Vdc; VOL = 0.4 Vdc; 125C | 3 |
| Output Drive Current, Sink | IOL | 0.9 | | | mAdc | VDD 10 Vdc; VOL = 0.5 Vdc; 125C | 3 |
| Output Drive Current, Sink | IOL | 2.4 | | | mAdc | VDD 15 Vdc; VOL = 1.5 Vdc; 125C | 3 |
| Input Current | Iin | -1 | | 1 | Adc | VDD 15 Vdc; 125C; printed as ±1.0 | 3 |
| Three-State Leakage Current | ITL | -3 | | 3 | Adc | VDD 15 Vdc; 125C; printed as ±3.0 | 3 |
| Quiescent Current (Per Package) | IDD | | | 5 | Adc | VDD 5.0 Vdc; per package; -55C | 3 |
| Quiescent Current (Per Package) | IDD | | | 10 | Adc | VDD 10 Vdc; per package; -55C | 3 |
| Quiescent Current (Per Package) | IDD | | | 20 | Adc | VDD 15 Vdc; per package; -55C | 3 |
## CAD (KiCad official)
- Symbol: `MC14076BDR2G`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `mc14076bdr2g-etched.step` / `mc14076bdr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mc14076bdr2g.step` / `mc14076bdr2g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588898801692659713) (8 pp, sha256 `df82d0401a9230af`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mc14076bdr2g-datasheet.pdf)