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Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	mc14011bdtr2g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
viewers	mc14011bdtr2g: viewers · Ray	1mo ago
mc14011bdtr2g-etched.fit.json	mc14011bdtr2g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
mc14011bdtr2g-etched.glb	mc14011bdtr2g: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bo… · Ray	14d ago
mc14011bdtr2g-etched.step	mc14011bdtr2g: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bo… · Ray	14d ago
mc14011bdtr2g.glb	Publish 0.1.0 · Ray	1mo ago
mc14011bdtr2g.kicad_mod	Publish 0.1.0 · Ray	1mo ago
mc14011bdtr2g.kicad_sym	Publish 0.1.0 · Ray	1mo ago
mc14011bdtr2g.lbr	Publish 0.1.0 · Ray	1mo ago
mc14011bdtr2g.step	Publish 0.1.0 · Ray	1mo ago
package.json	Publish 0.1.0 · Ray	1mo ago
page.json	mc14011bdtr2g: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bo… · Ray	14d ago
README.md	mc14011bdtr2g: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray	1mo ago

MC14011BDTR2G

onsemi · Gates · TSSOP-14

MC14011BDTR2G from onsemi, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IN_1A	input	Gate A input 1. CMOS logic input; VIL max 1.5/3.0/4.0 V and VIH min 3.5/7.0/11 V at VDD = 5/10/15 Vdc. Input current typ 10 pA.
2	IN_2A	input	Gate A input 2. CMOS logic input paired with pin 1 to feed NAND gate A whose output is pin 3.
3	OUT_A	output	Gate A NAND output = NOT(IN_1A AND IN_2A). Buffered CMOS output; source/sink capability roughly 0.51/0.88 mA typ at VDD = 5 V.
4	OUT_B	output	Gate B NAND output = NOT(IN_1B AND IN_2B). Buffered CMOS output.
5	IN_1B	input	Gate B input 1. CMOS logic input.
6	IN_2B	input	Gate B input 2. CMOS logic input paired with pin 5 to feed NAND gate B.
7	VSS	power_in	Negative supply / ground reference for all four gates. All voltages referenced to VSS.
8	IN_1C	input	Gate C input 1. CMOS logic input.
9	IN_2C	input	Gate C input 2. CMOS logic input paired with pin 8 to feed NAND gate C.
10	OUT_C	output	Gate C NAND output = NOT(IN_1C AND IN_2C). Buffered CMOS output.
11	OUT_D	output	Gate D NAND output = NOT(IN_1D AND IN_2D). Buffered CMOS output.
12	IN_1D	input	Gate D input 1. CMOS logic input.
13	IN_2D	input	Gate D input 2. CMOS logic input paired with pin 12 to feed NAND gate D.
14	VDD	power_in	Positive supply for all four gates. DC supply voltage range 3.0 to 18 Vdc (absolute max -0.5 to +18 V). Quiescent current typ 0.5 nA (5 V) to 1.5 nA (15 V) per package.

Key specifications

Parameter	Value
Manufacturer	onsemi
Package	TSSOP-14
Category	Logic
Pins	14

Ordering variants

Same part, different packaging or reel option.

MC14011BDTR2G
MC14011BDTR2GDTG
MC14011BDTR2GDR2G
MC14011BDTR2GDG

CAD (KiCad official)

Symbol: MC14011BDTR2G
Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
3D model: TSSOP-14 (KiCad packages3D, STEP)
3D model files: mc14011bdtr2g-etched.step / mc14011bdtr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc14011bdtr2g.step / mc14011bdtr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: onsemi datasheet (11 pp, sha256 9ca14896296eb906, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF