MC14011BDR2G

{
  "slug": "mc14011bdr2g",
  "version": "0.1.0",
  "type": "component",
  "description": "onsemi Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "mc14011bdr2g",
    "factory-2.0.0",
    "extractor-text"
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  "dependencies": {},
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    "type": "image",
    "path": "docs/hero.png"
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    "mc14011bdr2g.step",
    "mc14011bdr2g.lbr",
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    "docs/mc14011bdr2g-datasheet.pdf",
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    "viewers/footprint.html",
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  "component": {
    "mpn": "MC14011BDR2G",
    "manufacturer": "onsemi",
    "package": "SOIC-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586193205058809856",
    "parts": {
      "symbol": "mc14011bdr2g.kicad_sym",
      "footprint": "mc14011bdr2g.kicad_mod",
      "model_3d": "mc14011bdr2g-hero.glb",
      "model_3d_plain": "mc14011bdr2g.glb",
      "model_3d_step": "mc14011bdr2g-etched.step",
      "model_3d_step_plain": "mc14011bdr2g.step",
      "lbr": "mc14011bdr2g.lbr"
    },
    "distributor_links": {
      "lcsc": "C7278",
      "digikey": "MC14011BDR2GOSTR-ND",
      "mouser": "863-MC14011BDR2G"
    },
    "distributor_check": {
      "checked_at": "2026-10-09T18:10:36Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "MC14011BDR2GOSTR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "863-MC14011BDR2G",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "IN 1A",
        "type": "input",
        "description": "Input 1 of NAND gate A; unused inputs of NAND gates must be connected to VDD, and inputs must stay within VSS ≤ Vin ≤ VDD."
      },
      {
        "number": "2",
        "name": "IN 2A",
        "type": "input",
        "description": "Input 2 of NAND gate A; unused inputs of NAND gates must be connected to VDD, and inputs must stay within VSS ≤ Vin ≤ VDD."
      },
      {
        "number": "3",
        "name": "OUTA",
        "type": "output",
        "description": "Output of NAND gate A, buffered; output current is limited to 10 mA per pin."
      },
      {
        "number": "4",
        "name": "OUTB",
        "type": "output",
        "description": "Output of NAND gate B, buffered; output current is limited to 10 mA per pin."
      },
      {
        "number": "5",
        "name": "IN 1B",
        "type": "input",
        "description": "Input 1 of NAND gate B; unused inputs of NAND gates must be connected to VDD, and inputs must stay within VSS ≤ Vin ≤ VDD."
      },
      {
        "number": "6",
        "name": "IN 2B",
        "type": "input",
        "description": "Input 2 of NAND gate B; unused inputs of NAND gates must be connected to VDD, and inputs must stay within VSS ≤ Vin ≤ VDD."
      },
      {
        "number": "7",
        "name": "VSS",
        "type": "power_in",
        "description": "Negative supply / ground reference for all voltages in the datasheet (VSS = 0 V)."
      },
      {
        "number": "8",
        "name": "IN 1C",
        "type": "input",
        "description": "Input 1 of NAND gate C; unused inputs of NAND gates must be connected to VDD, and inputs must stay within VSS ≤ Vin ≤ VDD."
      },
      {
        "number": "9",
        "name": "IN 2C",
        "type": "input",
        "description": "Input 2 of NAND gate C; unused inputs of NAND gates must be connected to VDD, and inputs must stay within VSS ≤ Vin ≤ VDD."
      },
      {
        "number": "10",
        "name": "OUTC",
        "type": "output",
        "description": "Output of NAND gate C, buffered; output current is limited to 10 mA per pin."
      },
      {
        "number": "11",
        "name": "OUTD",
        "type": "output",
        "description": "Output of NAND gate D, buffered; output current is limited to 10 mA per pin."
      },
      {
        "number": "12",
        "name": "IN 1D",
        "type": "input",
        "description": "Input 1 of NAND gate D; unused inputs of NAND gates must be connected to VDD, and inputs must stay within VSS ≤ Vin ≤ VDD."
      },
      {
        "number": "13",
        "name": "IN 2D",
        "type": "input",
        "description": "Input 2 of NAND gate D; unused inputs of NAND gates must be connected to VDD, and inputs must stay within VSS ≤ Vin ≤ VDD."
      },
      {
        "number": "14",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply, rated 3.0 Vdc to 18 Vdc; absolute maximum −0.5 V to +18.0 V referenced to VSS."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The datasheet's pin-assignment drawings on page 2 lost their number-to-name alignment in text extrac; The page 2 pin-assignment blocks are labelled in scrambled order in the extracted text, so the block"
        ],
        "pages_sent": 11,
        "cost_usd": 0.0866,
        "at": "2026-10-09T18:08:33"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586193205058809856",
        "pages": 11,
        "sha256": "9ca14896296eb906",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
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        "zmin_mm": -0.0,
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        "checked": "2026-10-09",
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        "checked": "2026-10-21",
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}