component
MC14011BDR2G
Public Made by Adomby adom
onsemi Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMC14011BDR2G
onsemi · Logic Gates · SOIC-14
MC14011BDR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN 1A | input | Input 1 of NAND gate A; unused inputs of NAND gates must be connected to VDD, and inputs must stay within VSS ≤ Vin ≤ VDD. |
| 2 | IN 2A | input | Input 2 of NAND gate A; unused inputs of NAND gates must be connected to VDD, and inputs must stay within VSS ≤ Vin ≤ VDD. |
| 3 | OUTA | output | Output of NAND gate A, buffered; output current is limited to 10 mA per pin. |
| 4 | OUTB | output | Output of NAND gate B, buffered; output current is limited to 10 mA per pin. |
| 5 | IN 1B | input | Input 1 of NAND gate B; unused inputs of NAND gates must be connected to VDD, and inputs must stay within VSS ≤ Vin ≤ VDD. |
| 6 | IN 2B | input | Input 2 of NAND gate B; unused inputs of NAND gates must be connected to VDD, and inputs must stay within VSS ≤ Vin ≤ VDD. |
| 7 | VSS | power_in | Negative supply / ground reference for all voltages in the datasheet (VSS = 0 V). |
| 8 | IN 1C | input | Input 1 of NAND gate C; unused inputs of NAND gates must be connected to VDD, and inputs must stay within VSS ≤ Vin ≤ VDD. |
| 9 | IN 2C | input | Input 2 of NAND gate C; unused inputs of NAND gates must be connected to VDD, and inputs must stay within VSS ≤ Vin ≤ VDD. |
| 10 | OUTC | output | Output of NAND gate C, buffered; output current is limited to 10 mA per pin. |
| 11 | OUTD | output | Output of NAND gate D, buffered; output current is limited to 10 mA per pin. |
| 12 | IN 1D | input | Input 1 of NAND gate D; unused inputs of NAND gates must be connected to VDD, and inputs must stay within VSS ≤ Vin ≤ VDD. |
| 13 | IN 2D | input | Input 2 of NAND gate D; unused inputs of NAND gates must be connected to VDD, and inputs must stay within VSS ≤ Vin ≤ VDD. |
| 14 | VDD | power_in | Positive supply, rated 3.0 Vdc to 18 Vdc; absolute maximum −0.5 V to +18.0 V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
MC14011BDR2G - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
mc14011bdr2g-etched.step/mc14011bdr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc14011bdr2g.step/mc14011bdr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (11 pp, sha256
9ca14896296eb906, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).