component
MB85RS128BPNF-G-JNERE1
Public Made by Adomby adom
FUJITSU FRAM, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+122−8@@ -1,13 +1,132 @@ {+ "schema_version": 1,+ "type": "component", "slug": "mb85rs128bpnf-g-jnere1",+ "title": "MB85RS128BPNF-G-JNERE1",+ "brief": "FUJITSU FRAM, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "FUJITSU FRAM, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "memory", "mb85rs128bpnf-g-jnere1" ],+ "component": {+ "mpn": "MB85RS128BPNF-G-JNERE1",+ "manufacturer": "FUJITSU",+ "package": "SOP-8",+ "pin_count": 8,+ "category": "Memory",+ "subcategory": "FRAM",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586197201249325056",+ "parts": {+ "symbol": "mb85rs128bpnf-g-jnere1.kicad_sym",+ "footprint": "mb85rs128bpnf-g-jnere1.kicad_mod",+ "model_3d": "mb85rs128bpnf-g-jnere1.glb",+ "model_3d_step": "mb85rs128bpnf-g-jnere1.step",+ "lbr": "mb85rs128bpnf-g-jnere1.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "CS",+ "type": "input",+ "description": "Chip Select (active low). Device is selected/active when CS='L', deselected (standby) and SO is High-Z when CS='H'. Must be 'L' before inputting an op-code."+ },+ {+ "number": "2",+ "name": "SO",+ "type": "output",+ "description": "Serial Data Output. Outputs FRAM memory cell array and status register data synchronously to the falling edge of SCK. High-Z during standby."+ },+ {+ "number": "3",+ "name": "WP",+ "type": "input",+ "description": "Write Protect (active low). Controls writing to the status register in conjunction with the WPEN bit; see WRITING PROTECT section."+ },+ {+ "number": "4",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0 V)."+ },+ {+ "number": "5",+ "name": "SI",+ "type": "input",+ "description": "Serial Data Input. Op-code, address, and write data are input on SI, loaded synchronously to the rising edge of SCK."+ },+ {+ "number": "6",+ "name": "SCK",+ "type": "input",+ "description": "Serial Clock input for serial data I/O. SI is latched on the rising edge, SO is driven on the falling edge. Supports SPI mode 0 (CPOL=0, CPHA=0) and mode 3 (CPOL=1, CPHA=1). Up to 33 MHz (25 MHz for READ)."+ },+ {+ "number": "7",+ "name": "HOLD",+ "type": "input",+ "description": "Hold (active low). When HOLD='L', serial I/O is suspended without deselecting the device: SO becomes High-Z and SCK/SI are ignored. CS must remain 'L' during hold."+ },+ {+ "number": "8",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply voltage input, 2.7 V to 3.6 V. Operating current ~6 mA typ @ 33 MHz; standby ~9 uA typ."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586197201249325056",+ "pages": 36,+ "sha256": "7424f5d4f31e96a6",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 8,+ "described": 8,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "FUJITSU",+ "Package": "SOP-8",+ "Category": "Memory",+ "Pins": "8"+ }+ },+ "variants": [+ {+ "mpn": "MB85RS128BPNF-G-JNERE1",+ "kind": "packaging"+ }+ ],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "mb85rs128bpnf-g-jnere1"+ ],+ "discovery_pitch": "MB85RS128BPNF-G-JNERE1 (FUJITSU) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +144,5 @@ "docs/mb85rs128bpnf-g-jnere1-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }