component
MAX96752GTN
Public Made by Adomby adom
ADI(亚德诺)/MAXIM(美信) Serializers, Deserializers, TQFN-56-EP(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"schema_version": 1,
"type": "component",
"slug": "max96752gtn",
"title": "MAX96752GTN",
"brief": "ADI(亚德诺)/MAXIM(美信) Serializers, Deserializers, TQFN-56-EP(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"interface",
"max96752gtn",
"factory-2.0.0",
"extractor-text"
],
"component": {
"mpn": "MAX96752GTN",
"manufacturer": "ADI(亚德诺)/MAXIM(美信)",
"package": "TQFN-56-EP(8x8)",
"pin_count": 57,
"category": "Interface",
"subcategory": "Serializers, Deserializers",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8604422450184663040",
"parts": {
"symbol": "max96752gtn.kicad_sym",
"footprint": "max96752gtn.kicad_mod",
"model_3d": "max96752gtn-hero.glb",
"model_3d_plain": "max96752gtn-etched.glb",
"model_3d_step": "max96752gtn-etched.step",
"model_3d_step_plain": "max96752gtn.step",
"lbr": "max96752gtn.lbr"
},
"distributor_links": {
"lcsc": "C25598951"
},
"distributor_check": {
"checked_at": "2026-10-19T09:43:27Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": null,
"status": "no match"
},
"mouser": {
"pn": null,
"status": "no match"
}
},
"pins": [
{
"number": "1",
"name": "VREG",
"type": "power_in",
"description": "Internal 1.0V digital regulator supply; if the regulator is used connect a 1.8V ±5% supply, otherwise make no connection."
},
{
"number": "2",
"name": "VREGA",
"type": "power_in",
"description": "Internal 1.0V analog regulator supply; if the regulator is used connect a 1.8V ±5% supply, otherwise make no connection."
},
{
"number": "3",
"name": "SIOB-",
"type": "input",
"description": "Inverted twisted-pair GMSL2 serial-data input 2; SIO inputs are rated (VDD18 - 1.1V) to VDD18 when active and -0.3V to +1.1V when inactive."
},
{
"number": "4",
"name": "SIOB+",
"type": "input",
"description": "Noninverted coax/twisted-pair GMSL2 serial-data input 2; SIO inputs are rated (VDD18 - 1.1V) to VDD18 when active and -0.3V to +1.1V when inactive."
},
{
"number": "5",
"name": "VDD18",
"type": "power_in",
"description": "1.8V ±5% I/O supply (recommended range 1.7V to 1.9V)."
},
{
"number": "6",
"name": "VDD18",
"type": "power_in",
"description": "1.8V ±5% I/O supply (recommended range 1.7V to 1.9V)."
},
{
"number": "7",
"name": "RSVD",
"type": "unconnected",
"description": "Reserved; make no electrical connection to this pin."
},
{
"number": "8",
"name": "SDA_RX",
"type": "bidirectional",
"description": "Primary control-channel I2C serial data input/open-drain output or UART receive, with an internal 40kΩ pullup to VDDIO; alternate function GPIO14."
},
{
"number": "9",
"name": "SCL_TX",
"type": "bidirectional",
"description": "Primary control-channel I2C serial clock input/open-drain output or UART transmit, with an internal 40kΩ pullup to VDDIO; alternate function GPIO15."
},
{
"number": "10",
"name": "VDDA",
"type": "power_in",
"description": "Core analog 1V supply: connect 1.0V ±5% if not using the VREGA regulator; do not apply a voltage if the regulator is used."
},
{
"number": "11",
"name": "GPIO09/CXTP",
"type": "bidirectional",
"description": "CXTP input with 1MΩ pulldown, latched at power-up (high selects coax, low selects twisted-pair); after power-up it is GPO09, with alternate BNE and SS1 functions."
},
{
"number": "12",
"name": "GPIO10",
"type": "bidirectional",
"description": "Configurable GPIO, high impedance with unconnected input after power-up; alternate RO (SPI mode select with 1MΩ pulldown) or SS2 function; leave unconnected when not used."
},
{
"number": "13",
"name": "LOCK",
"type": "output",
"description": "Open-drain lock indication output with an internal 40kΩ pullup to VDDIO."
},
{
"number": "14",
"name": "ERRB",
"type": "output",
"description": "Open-drain error indication output with an internal 40kΩ pullup to VDDIO; low indicates a data error or interrupt, and it is high when PWDNB is low."
},
{
"number": "15",
"name": "X1/OSC",
"type": "input",
"description": "Crystal or oscillator input; connect to a 25MHz crystal or a 25MHz external clock source (±200ppm frequency accuracy)."
},
{
"number": "16",
"name": "X2",
"type": "passive",
"description": "Crystal input; connect one terminal of a 25MHz crystal here and a load capacitor from X1/OSC to ground."
},
{
"number": "17",
"name": "RSVD",
"type": "unconnected",
"description": "Reserved; make no electrical connection to this pin."
},
{
"number": "18",
"name": "XRES",
"type": "passive",
"description": "Used to calibrate SIO output driver swings; connect an external 402Ω ±1% resistor between XRES and ground."
},
{
"number": "19",
"name": "GPIO01/I2CSEL",
"type": "bidirectional",
"description": "I2CSEL latch-on input with 1MΩ pulldown (high selects I2C, low selects UART at power-up); after power-up it is GPO01 by default, with alternate VS vertical-sync push-pull output."
},
{
"number": "20",
"name": "VDD18",
"type": "power_in",
"description": "1.8V ±5% I/O supply (recommended range 1.7V to 1.9V)."
},
{
"number": "21",
"name": "SIOA+",
"type": "input",
"description": "Noninverted coax/twisted-pair GMSL2 serial-data input 1; SIO inputs are rated (VDD18 - 1.1V) to VDD18 when active and -0.3V to +1.1V when inactive."
},
{
"number": "22",
"name": "SIOA-",
"type": "input",
"description": "Inverted twisted-pair GMSL2 serial-data input 1; SIO inputs are rated (VDD18 - 1.1V) to VDD18 when active and -0.3V to +1.1V when inactive."
},
{
"number": "23",
"name": "PWDNB",
"type": "input",
"description": "Active-low power-down input with an internal 1MΩ pulldown to ground; set low to enter power-down mode."
},
{
"number": "24",
"name": "SD/ADD0",
"type": "bidirectional",
"description": "ADD0 latch-on address-select input with 1MΩ pulldown; after power-up it is the I2S/TDM serial-data push-pull output (SD), with alternate GPO11."
},
{
"number": "25",
"name": "SCK/ADD1",
"type": "bidirectional",
"description": "ADD1 latch-on address-select input with 1MΩ pulldown; after power-up it is the I2S/TDM serial-clock push-pull output (SCK), with alternate GPO12."
},
{
"number": "26",
"name": "WS/ADD2",
"type": "bidirectional",
"description": "ADD2 latch-on address-select input with 1MΩ pulldown; after power-up it is the I2S/TDM word-select push-pull output (WS), with alternate GPO13."
},
{
"number": "27",
"name": "SDIR",
"type": "bidirectional",
"description": "I2S/TDM serial-data input with 1MΩ pulldown supporting reverse audio; alternate functions GPIO06 and pass-through I2C2/UART2 receive (SDA2_RX2)."
},
{
"number": "28",
"name": "SCKIR",
"type": "bidirectional",
"description": "I2S/TDM serial-clock input with 1MΩ pulldown supporting reverse audio; alternate function GPIO07."
},
{
"number": "29",
"name": "WSIR",
"type": "bidirectional",
"description": "I2S/TDM word-select input with 1MΩ pulldown supporting reverse audio; alternate functions GPIO08 and pass-through I2C2/UART2 transmit (SCL2_TX2)."
},
{
"number": "30",
"name": "TxOUT_A3+",
"type": "output",
"description": "LVDS data output port A, lane 3 positive; port A supports up to 150MHz pixel clock, and unused OLDI ports should be powered down via register OLDI2."
},
{
"number": "31",
"name": "TxOUT_A3-",
"type": "output",
"description": "LVDS data output port A, lane 3 negative; port A supports up to 150MHz pixel clock, and unused OLDI ports should be powered down via register OLDI2."
},
{
"number": "32",
"name": "TxOUT_A2+",
"type": "output",
"description": "LVDS data output port A, lane 2 positive; port A supports up to 150MHz pixel clock, and unused OLDI ports should be powered down via register OLDI2."
},
{
"number": "33",
"name": "TxOUT_A2-",
"type": "output",
"description": "LVDS data output port A, lane 2 negative; port A supports up to 150MHz pixel clock, and unused OLDI ports should be powered down via register OLDI2."
},
{
"number": "34",
"name": "TxCLK_OUTA+",
"type": "output",
"description": "LVDS clock output port A, positive; port A supports up to 150MHz pixel clock."
},
{
"number": "35",
"name": "TxCLK_OUTA-",
"type": "output",
"description": "LVDS clock output port A, negative; port A supports up to 150MHz pixel clock."
},
{
"number": "36",
"name": "TxOUT_A1+",
"type": "output",
"description": "LVDS data output port A, lane 1 positive; port A supports up to 150MHz pixel clock, and unused OLDI ports should be powered down via register OLDI2."
},
{
"number": "37",
"name": "TxOUT_A1-",
"type": "output",
"description": "LVDS data output port A, lane 1 negative; port A supports up to 150MHz pixel clock, and unused OLDI ports should be powered down via register OLDI2."
},
{
"number": "38",
"name": "TxOUT_A0+",
"type": "output",
"description": "LVDS data output port A, lane 0 positive; port A supports up to 150MHz pixel clock, and unused OLDI ports should be powered down via register OLDI2."
},
{
"number": "39",
"name": "TxOUT_A0-",
"type": "output",
"description": "LVDS data output port A, lane 0 negative; port A supports up to 150MHz pixel clock, and unused OLDI ports should be powered down via register OLDI2."
},
{
"number": "40",
"name": "GPIO03",
"type": "bidirectional",
"description": "Configurable GPIO, high impedance with unconnected input after power-up; alternate SPI MOSI or pass-through I2C1/UART1 receive (SDA1_RX1) with internal 40kΩ pullup to VDDIO."
},
{
"number": "41",
"name": "GPIO04",
"type": "bidirectional",
"description": "Configurable GPIO, high impedance with unconnected input after power-up; alternate SPI MISO function (1MΩ pulldown when used as main input)."
},
{
"number": "42",
"name": "GPIO05",
"type": "bidirectional",
"description": "Configurable GPIO, high impedance with unconnected input after power-up; alternate SPI SCLK or pass-through I2C1/UART1 transmit (SCL1_TX1) with internal 40kΩ pullup to VDDIO."
},
{
"number": "43",
"name": "VDD18",
"type": "power_in",
"description": "1.8V ±5% I/O supply (recommended range 1.7V to 1.9V)."
},
{
"number": "44",
"name": "VDDIO",
"type": "power_in",
"description": "1.8V to 3.3V I/O supply for GPIO and control pins (1.7V to 1.9V at 1.8V nominal, 3.0V to 3.6V at 3.3V nominal)."
},
{
"number": "45",
"name": "GPIO02",
"type": "bidirectional",
"description": "Configurable GPIO, high impedance with unconnected input after power-up; alternate WMD watermark-detect push-pull output or MS UART mode select with 1MΩ pulldown."
},
{
"number": "46",
"name": "TxOUT_B3+",
"type": "output",
"description": "LVDS data output port B, lane 3 positive; port B supports up to 150MHz pixel clock."
},
{
"number": "47",
"name": "TxOUT_B3-",
"type": "output",
"description": "LVDS data output port B, lane 3 negative; port B supports up to 150MHz pixel clock."
},
{
"number": "48",
"name": "TxOUT_B2+",
"type": "output",
"description": "LVDS data output port B, lane 2 positive; port B supports up to 150MHz pixel clock."
},
{
"number": "49",
"name": "TxOUT_B2-",
"type": "output",
"description": "LVDS data output port B, lane 2 negative; port B supports up to 150MHz pixel clock."
},
{
"number": "50",
"name": "TxCLK_OUTB+",
"type": "output",
"description": "LVDS clock output port B, positive; port B supports up to 150MHz pixel clock."
},
{
"number": "51",
"name": "TxCLK_OUTB-",
"type": "output",
"description": "LVDS clock output port B, negative; port B supports up to 150MHz pixel clock."
},
{
"number": "52",
"name": "TxOUT_B1+",
"type": "output",
"description": "LVDS data output port B, lane 1 positive; port B supports up to 150MHz pixel clock."
},
{
"number": "53",
"name": "TxOUT_B1-",
"type": "output",
"description": "LVDS data output port B, lane 1 negative; port B supports up to 150MHz pixel clock."
},
{
"number": "54",
"name": "TxOUT_B0+",
"type": "output",
"description": "LVDS data output port B, lane 0 positive; port B supports up to 150MHz pixel clock."
},
{
"number": "55",
"name": "TxOUT_B0-",
"type": "output",
"description": "LVDS data output port B, lane 0 negative; port B supports up to 150MHz pixel clock."
},
{
"number": "56",
"name": "VDDD",
"type": "power_in",
"description": "Core digital 1V supply: connect 1.0V ±5% if not using the VREG regulator; do not apply a voltage if the regulator is used."
},
{
"number": "57",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The MPN MAX96752GTN is ordered as MAX96752GTN/V+ (56-Lead TQFN-EP) and MAX96752GTN/VY+ (56-Lead TQFN; The exposed pad is printed as 'EP' in the datasheet rather than a numeric pin, so it is listed as 'E; The Pin Configuration drawing on page 17 is garbled in the extracted text, so the pinout was taken f",
"exposed pad 57 added from the footprint",
"dropped thermal pad ['EP'] absent from footprint"
],
"pages_sent": 56,
"cost_usd": 0.3316,
"at": "2026-10-19T09:43:11"
},
"datasheet": {
"url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8604422450184663040",
"pages": 159,
"sha256": "e293c90a440b2f23",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 57,
"described": 57,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "max96752gtn.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
8,
8,
1
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "54eb482f12c9d8b70c1bfc78306a1c34f412f3556e225cbd097840e5abdb7981",
"checked": "2026-10-19",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "max96752gtn-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
8,
8,
1
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "681a7c1c83b8273d1eaf264b84bca847489e226247cfcad07481a71fdd086d69",
"checked": "2026-10-19",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "ADI(亚德诺)/MAXIM(美信)",
"Package": "TQFN-56-EP(8x8)",
"Category": "Interface",
"Pins": "57"
},
"characteristics": {
"version": 1,
"source": "datasheet",
"datasheet_sha256": "e293c90a440b2f23cacb65ec0a7b53b78810038b782e64d6b5d85fb50e36a3a3",
"rows": [
{
"name": "VDDIO supply voltage (absolute maximum)",
"symbol": "VDDIO",
"kind": "absolute_maximum",
"unit": "V",
"min": -0.3,
"typ": null,
"max": 3.9,
"conditions": "",
"source_page": 8,
"source": "datasheet"
},
{
"name": "VDD18 supply voltage (absolute maximum)",
"symbol": "VDD18",
"kind": "absolute_maximum",
"unit": "V",
"min": -0.3,
"typ": null,
"max": 2,
"conditions": "",
"source_page": 8,
"source": "datasheet"
},
{
"name": "VDDD, VDDA supply voltage (absolute maximum)",
"symbol": "VDDD, VDDA",
"kind": "absolute_maximum",
"unit": "V",
"min": -0.3,
"typ": null,
"max": 1.1,
"conditions": "",
"source_page": 8,
"source": "datasheet"
},
{
"name": "VREG, VREGA supply voltage (absolute maximum)",
"symbol": "VREG, VREGA",
"kind": "absolute_maximum",
"unit": "V",
"min": -0.3,
"typ": null,
"max": 2,
"conditions": "",
"source_page": 8,
"source": "datasheet"
},
{
"name": "SIO__ inactive state voltage (absolute maximum)",
"symbol": "SIO__",
"kind": "absolute_maximum",
"unit": "V",
"min": -0.3,
"typ": null,
"max": 1.1,
"conditions": "Inactive state (Note a)",
"source_page": 8,
"source": "datasheet"
},
{
"name": "XRES, X2 voltage (absolute maximum, minimum)",
"symbol": "XRES, X2",
"kind": "absolute_maximum",
"unit": "V",
"min": -0.3,
"typ": null,
"max": null,
"conditions": "",
"source_page": 8,
"source": "datasheet"
},
{
"name": "All other pins voltage (absolute maximum, minimum)",
"symbol": "",
"kind": "absolute_maximum",
"unit": "V",
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