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MAX96752GTN

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ADI(亚德诺)/MAXIM(美信) Serializers, Deserializers, TQFN-56-EP(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MAX96752GTN

ADI(亚德诺)/MAXIM(美信) · Serializers, Deserializers · TQFN-56-EP(8x8)

MAX96752GTN from ADI(亚德诺)/MAXIM(美信), in a TQFN-56-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VREG power_in Internal 1.0V digital regulator supply; if the regulator is used connect a 1.8V ±5% supply, otherwise make no connection.
2 VREGA power_in Internal 1.0V analog regulator supply; if the regulator is used connect a 1.8V ±5% supply, otherwise make no connection.
3 SIOB- input Inverted twisted-pair GMSL2 serial-data input 2; SIO inputs are rated (VDD18 - 1.1V) to VDD18 when active and -0.3V to +1.1V when inactive.
4 SIOB+ input Noninverted coax/twisted-pair GMSL2 serial-data input 2; SIO inputs are rated (VDD18 - 1.1V) to VDD18 when active and -0.3V to +1.1V when inactive.
5 VDD18 power_in 1.8V ±5% I/O supply (recommended range 1.7V to 1.9V).
6 VDD18 power_in 1.8V ±5% I/O supply (recommended range 1.7V to 1.9V).
7 RSVD unconnected Reserved; make no electrical connection to this pin.
8 SDA_RX bidirectional Primary control-channel I2C serial data input/open-drain output or UART receive, with an internal 40kΩ pullup to VDDIO; alternate function GPIO14.
9 SCL_TX bidirectional Primary control-channel I2C serial clock input/open-drain output or UART transmit, with an internal 40kΩ pullup to VDDIO; alternate function GPIO15.
10 VDDA power_in Core analog 1V supply: connect 1.0V ±5% if not using the VREGA regulator; do not apply a voltage if the regulator is used.
11 GPIO09/CXTP bidirectional CXTP input with 1MΩ pulldown, latched at power-up (high selects coax, low selects twisted-pair); after power-up it is GPO09, with alternate BNE and SS1 functions.
12 GPIO10 bidirectional Configurable GPIO, high impedance with unconnected input after power-up; alternate RO (SPI mode select with 1MΩ pulldown) or SS2 function; leave unconnected when not used.
13 LOCK output Open-drain lock indication output with an internal 40kΩ pullup to VDDIO.
14 ERRB output Open-drain error indication output with an internal 40kΩ pullup to VDDIO; low indicates a data error or interrupt, and it is high when PWDNB is low.
15 X1/OSC input Crystal or oscillator input; connect to a 25MHz crystal or a 25MHz external clock source (±200ppm frequency accuracy).
16 X2 passive Crystal input; connect one terminal of a 25MHz crystal here and a load capacitor from X1/OSC to ground.
17 RSVD unconnected Reserved; make no electrical connection to this pin.
18 XRES passive Used to calibrate SIO output driver swings; connect an external 402Ω ±1% resistor between XRES and ground.
19 GPIO01/I2CSEL bidirectional I2CSEL latch-on input with 1MΩ pulldown (high selects I2C, low selects UART at power-up); after power-up it is GPO01 by default, with alternate VS vertical-sync push-pull output.
20 VDD18 power_in 1.8V ±5% I/O supply (recommended range 1.7V to 1.9V).
21 SIOA+ input Noninverted coax/twisted-pair GMSL2 serial-data input 1; SIO inputs are rated (VDD18 - 1.1V) to VDD18 when active and -0.3V to +1.1V when inactive.
22 SIOA- input Inverted twisted-pair GMSL2 serial-data input 1; SIO inputs are rated (VDD18 - 1.1V) to VDD18 when active and -0.3V to +1.1V when inactive.
23 PWDNB input Active-low power-down input with an internal 1MΩ pulldown to ground; set low to enter power-down mode.
24 SD/ADD0 bidirectional ADD0 latch-on address-select input with 1MΩ pulldown; after power-up it is the I2S/TDM serial-data push-pull output (SD), with alternate GPO11.
25 SCK/ADD1 bidirectional ADD1 latch-on address-select input with 1MΩ pulldown; after power-up it is the I2S/TDM serial-clock push-pull output (SCK), with alternate GPO12.
26 WS/ADD2 bidirectional ADD2 latch-on address-select input with 1MΩ pulldown; after power-up it is the I2S/TDM word-select push-pull output (WS), with alternate GPO13.
27 SDIR bidirectional I2S/TDM serial-data input with 1MΩ pulldown supporting reverse audio; alternate functions GPIO06 and pass-through I2C2/UART2 receive (SDA2_RX2).
28 SCKIR bidirectional I2S/TDM serial-clock input with 1MΩ pulldown supporting reverse audio; alternate function GPIO07.
29 WSIR bidirectional I2S/TDM word-select input with 1MΩ pulldown supporting reverse audio; alternate functions GPIO08 and pass-through I2C2/UART2 transmit (SCL2_TX2).
30 TxOUT_A3+ output LVDS data output port A, lane 3 positive; port A supports up to 150MHz pixel clock, and unused OLDI ports should be powered down via register OLDI2.
31 TxOUT_A3- output LVDS data output port A, lane 3 negative; port A supports up to 150MHz pixel clock, and unused OLDI ports should be powered down via register OLDI2.
32 TxOUT_A2+ output LVDS data output port A, lane 2 positive; port A supports up to 150MHz pixel clock, and unused OLDI ports should be powered down via register OLDI2.
33 TxOUT_A2- output LVDS data output port A, lane 2 negative; port A supports up to 150MHz pixel clock, and unused OLDI ports should be powered down via register OLDI2.
34 TxCLK_OUTA+ output LVDS clock output port A, positive; port A supports up to 150MHz pixel clock.
35 TxCLK_OUTA- output LVDS clock output port A, negative; port A supports up to 150MHz pixel clock.
36 TxOUT_A1+ output LVDS data output port A, lane 1 positive; port A supports up to 150MHz pixel clock, and unused OLDI ports should be powered down via register OLDI2.
37 TxOUT_A1- output LVDS data output port A, lane 1 negative; port A supports up to 150MHz pixel clock, and unused OLDI ports should be powered down via register OLDI2.
38 TxOUT_A0+ output LVDS data output port A, lane 0 positive; port A supports up to 150MHz pixel clock, and unused OLDI ports should be powered down via register OLDI2.
39 TxOUT_A0- output LVDS data output port A, lane 0 negative; port A supports up to 150MHz pixel clock, and unused OLDI ports should be powered down via register OLDI2.
40 GPIO03 bidirectional Configurable GPIO, high impedance with unconnected input after power-up; alternate SPI MOSI or pass-through I2C1/UART1 receive (SDA1_RX1) with internal 40kΩ pullup to VDDIO.
41 GPIO04 bidirectional Configurable GPIO, high impedance with unconnected input after power-up; alternate SPI MISO function (1MΩ pulldown when used as main input).
42 GPIO05 bidirectional Configurable GPIO, high impedance with unconnected input after power-up; alternate SPI SCLK or pass-through I2C1/UART1 transmit (SCL1_TX1) with internal 40kΩ pullup to VDDIO.
43 VDD18 power_in 1.8V ±5% I/O supply (recommended range 1.7V to 1.9V).
44 VDDIO power_in 1.8V to 3.3V I/O supply for GPIO and control pins (1.7V to 1.9V at 1.8V nominal, 3.0V to 3.6V at 3.3V nominal).
45 GPIO02 bidirectional Configurable GPIO, high impedance with unconnected input after power-up; alternate WMD watermark-detect push-pull output or MS UART mode select with 1MΩ pulldown.
46 TxOUT_B3+ output LVDS data output port B, lane 3 positive; port B supports up to 150MHz pixel clock.
47 TxOUT_B3- output LVDS data output port B, lane 3 negative; port B supports up to 150MHz pixel clock.
48 TxOUT_B2+ output LVDS data output port B, lane 2 positive; port B supports up to 150MHz pixel clock.
49 TxOUT_B2- output LVDS data output port B, lane 2 negative; port B supports up to 150MHz pixel clock.
50 TxCLK_OUTB+ output LVDS clock output port B, positive; port B supports up to 150MHz pixel clock.
51 TxCLK_OUTB- output LVDS clock output port B, negative; port B supports up to 150MHz pixel clock.
52 TxOUT_B1+ output LVDS data output port B, lane 1 positive; port B supports up to 150MHz pixel clock.
53 TxOUT_B1- output LVDS data output port B, lane 1 negative; port B supports up to 150MHz pixel clock.
54 TxOUT_B0+ output LVDS data output port B, lane 0 positive; port B supports up to 150MHz pixel clock.
55 TxOUT_B0- output LVDS data output port B, lane 0 negative; port B supports up to 150MHz pixel clock.
56 VDDD power_in Core digital 1V supply: connect 1.0V ±5% if not using the VREG regulator; do not apply a voltage if the regulator is used.
57 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer ADI(亚德诺)/MAXIM(美信)
Package TQFN-56-EP(8x8)
Category Interface
Pins 57

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDDIO supply voltage (absolute maximum) VDDIO -0.3 3.9 V 8
VDD18 supply voltage (absolute maximum) VDD18 -0.3 2 V 8
VDDD, VDDA supply voltage (absolute maximum) VDDD, VDDA -0.3 1.1 V 8
VREG, VREGA supply voltage (absolute maximum) VREG, VREGA -0.3 2 V 8
SIO__ inactive state voltage (absolute maximum) SIO__ -0.3 1.1 V Inactive state (Note a) 8
XRES, X2 voltage (absolute maximum, minimum) XRES, X2 -0.3 V 8
All other pins voltage (absolute maximum, minimum) -0.3 V 8
Storage Temperature Range -40 150 °C 8
Soldering Temperature (Reflow) 260 °C 8
VDD18 supply range VDD18 1.7 1.8 1.9 V 23
VDDIO supply range (nominal 1.8 V) VDDIO 1.7 1.8 1.9 V Nominal voltage 1.8 V 23
VDDIO supply range (nominal 3.3 V) VDDIO 3 3.3 3.6 V Nominal voltage 3.3 V 23
VDDD, VDDA supply range (if driven externally) VDDD, VDDA 0.95 1 1.05 V 23
VREG, VREGA supply range (if regulators used) VREG, VREGA 1.7 1.8 1.9 V 23
Maximum supply noise VDD18 VDD18 25 mVP-P Supply noise < 1MHz 23
Maximum supply noise VDDIO (nominal 1.8 V) VDDIO 50 mVP-P Nominal 1.8 V; supply noise < 1MHz 23
Maximum supply noise VDDIO (nominal 3.3 V) VDDIO 100 mVP-P Nominal 3.3 V; supply noise < 1MHz 23
Maximum supply noise VDDD, VDDA VDDD, VDDA 25 mVP-P Supply noise < 1MHz 23
Operating Junction Temperature TJ -40 125 °C 23
Supply Current (VDD18) IDD 125 180 mA 148.5MHz PCLK, dual OLDI output at 74.25MHz, color bar pattern (Note 2) 11
Supply Current (VDDD) IDD 83 250 mA 148.5MHz PCLK, dual OLDI output at 74.25MHz, color bar pattern (Note 2) 11
Supply Current (VDDA) IDD 7 15 mA 148.5MHz PCLK, dual OLDI output at 74.25MHz, color bar pattern (Note 2) 11
Supply Current (VREG) IDD 75 250 mA 148.5MHz PCLK, dual OLDI output at 74.25MHz, color bar pattern (Note 2, Note 3) 11
Supply Current (VREGA) IDD 8 20 mA 148.5MHz PCLK, dual OLDI output at 74.25MHz, color bar pattern (Note 2, Note 3) 11
Maximum VDDIO Supply Current (VDDIO at 1.9V) IDDIO 44 μA/MHz Per GPIO toggling at 50 MHz, CL = 10pF 11
Maximum VDDIO Supply Current (VDDIO at 3.6V) IDDIO 81 μA/MHz Per GPIO toggling at 50 MHz, CL = 10pF 11
Maximum Power-Down Current (VDDIO) IDD 5 μA VDDIO at 3.6V, TA = 105ºC 11
Maximum Power-Down Current (VDD18) IDD 37 μA VDD18 at 1.9V, TA = 105ºC 11
Maximum Power-Down Current (VDDD) IDD 15 μA VDDD at 1.05V, TA = 105ºC 11
Maximum Power-Down Current (VDDA) IDD 10 μA VDDA at 1.05V, TA = 105ºC 11
Output Voltage Swing (Single-Ended) VO 190 250 310 mV RL = 100Ω ±1% 9
Output Voltage Swing (Differential) VODT 380 500 620 mV RL = 100Ω ±1%, peak-to-peak differential voltage 9
Termination Resistance (Internal) RT 50 55 60 Ω Any Pin to VDD18 9
Differential Output Voltage VOD (LVDS) VOD 250 450 mV Full swing enabled 9
Differential Output Voltage VOD (LVDS, half swing) VOD 125 225 mV Half swing enabled 9
Common-Mode Voltage (LVDS) VOS 1.125 1.375 V 9
Output Short Circuit Current IOS -15 15 mA Tx_ pin shorted to 0V or VDD18 9
Magnitude of Differential Output Short Circuit Current IOSD 15 mA Differential output pair shorted together 9
Output High Impedance Current IOZ -0.5 0.5 μA Output powered down, Tx_ pin shorted to 0V or VDD18 9
Change in VOD Between Complementary Output States (serial) ΔVOD 25 mV RL = 100Ω ±1%, /VOD(H) - VOD(L)/ 9
Change in VOD Between Complementary Output States (LVDS) ΔVOD 25 mV 9
Change in VOS Between Complementary Output States (LVDS) ΔVOS 25 mV 9
Low-Level Output Voltage (I/O pins) VOL 0.4 V IOL = 4mA 9
Input Current (I/O pins) IIN 1 μA All pullup/pulldown devices disabled. VIN = 0V to VDDIO 10
Input Current (PWDNB) IIN 6 μA VIN = 0V to VDDIO 10
Lock Time tLOCK 50 ms (Note 4) (Note 6) 12
PWDNB Hold Time tHOLD_PWDNB 1 ms The minimum duration PWDNB must be held LOW to reset the chip 12
GMSL Reverse Channel Transmitter Rise/Fall Time tR, tF 2300 ps 20% to 80%, VO = 250mV, RL = 100Ω 12
Total Serial Output p-p Jitter tTSOJ2 0.25 UI PRBS7, single-ended or differential output 12
LVDS Clock Frequency fTXCLKOUT 6.45 150 MHz Single OLDI output (Note 2) 12
LVDS Output Rise Time tR 170 350 ps From 20% to 80%, CL = 5pF, RL = 100Ω (Note 2) 12
LVDS Output Fall Time tF 170 350 ps From 20% to 80%, CL = 5pF, RL = 100Ω (Note 2) 12
LVDS Output Jitter 110 ps p-p fTXCLKOUT = 150MHz, BER = 10-12 12
LVDS Output Enable Time tLVEN 50 μs Measured from last bit of UART packet that enables LVDS to output amplitude crossing 250mV (Note 2) 12
LVDS Output Disable Time tLVDS 50 μs Measured from last bit of UART packet that enables LVDS to output amplitude crossing 0V (Note 2) 12
I2C/UART Output Fall Time tF 150 ns 70% to 30%, CL = 20pF to 100pF, 1kΩ pullup to VDDIO (Note 2) 12
I2C/UART Wake Time 1.1 4 ms From power-up or rising edge of PWDNB to local register access 12
Thermal Resistance Junction-to-Ambient (four-layer board) θJA 25 °C/W Four-layer board, still air, JESD51-7 8
Thermal Resistance Junction-to-Case θJC 1 °C/W Four-layer board, still air, JESD51-7 8

CAD (KiCad official)

  • Symbol: MAX96752GTN
  • Footprint: Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm
  • 3D model: TQFN-56-EP(8x8) (KiCad packages3D, STEP)
  • 3D model files: max96752gtn-etched.step / max96752gtn-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max96752gtn.step / max96752gtn.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ADI(亚德诺)/MAXIM(美信) datasheet (159 pp, sha256 e293c90a440b2f23, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF