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MAX6371KA+T

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Analog Devices Inc Maxim Integrated Supervisor And Reset ICs, SOT-23-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MAX6371KA+T

Analog Devices Inc Maxim Integrated · Supervisor And Reset ICs · SOT-23-8

MAX6371KA+T from Analog Devices Inc Maxim Integrated, in a SOT-23-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 WDI input Watchdog input: if WDI stays either high or low for the full watchdog timeout period tWD, WDO pulses, and the internal timer clears on each rising or falling WDI edge.
2 GND power_in Ground reference for the device, with all voltage limits specified with respect to GND.
3 N.C. unconnected Not connected; the datasheet says not to make any connection to this pin.
4 SET0 input Logic input that selects the startup delay and watchdog timeout periods together with SET1 and SET2, per Table 1; must stay within -0.3V to (VCC + 0.3V).
5 SET1 input Logic input that selects the startup delay and watchdog timeout periods together with SET0 and SET2, per Table 1; must stay within -0.3V to (VCC + 0.3V).
6 SET2 input Logic input that selects the startup delay and watchdog timeout periods together with SET0 and SET1, per Table 1; must stay within -0.3V to (VCC + 0.3V).
7 WDO output Active-low watchdog output that pulses low for tWDO (100ms to 300ms on the open-drain MAX6371) when the watchdog times out, and requires a pull-up resistor (up to +5.5V).
8 VCC power_in Supply voltage, +2.5V to +5.5V.

Key specifications

Parameter Value
Manufacturer Analog Devices Inc Maxim Integrated
Package SOT-23-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Absolute maximum VCC terminal voltage VCC -0.3 6 V Terminal voltage with respect to GND 2
Absolute maximum WDI terminal voltage WDI -0.3 6 V Terminal voltage with respect to GND 2
Absolute maximum WDO terminal voltage (open drain) WDO -0.3 6 V Open Drain: MAX6369/71/73 2
Absolute maximum SET0, SET1, SET2 terminal voltage SET0, SET1, SET2 -0.3 V Upper limit printed as (VCC + 0.3V) 2
Maximum current, any pin (input/output) 20 mA Input/output 2
Operating temperature range -40 125 °C 2
Storage temperature range -65 150 °C 2
Junction temperature 150 °C 2
Lead temperature (soldering) 300 °C Soldering, 10s 2
Soldering temperature (reflow) 260 °C Lead(Pb)-free 2
Soldering temperature (reflow) 240 °C Containing lead (Pb) 2
Operating voltage range VCC 2.5 5.5 V 2
Supply current ICC 8 20 µA No load, TA = -40°C to +85°C 2
Supply current ICC 10 22 µA No load, TA = -40°C to +125°C 2
Input high voltage VIH 0.8 x VCC WDI, SET0, SET1, SET2 2
Input low voltage VIL 0.8 V VCC ≥ 3.3V, TA = -40°C to +85°C 2
Input low voltage VIL 0.6 V VCC ≥ 3.3V, TA = -40°C to +125°C 2
Input low voltage VIL 0.4 V VCC ≥ 2.5V, TA = -40°C to +125°C 2
Logic input current -10 0 10 nA VWDI or VSET_ = 0V or VCC 2
WDO output low voltage VOL 0.3 V ISINK = 1.2mA, VCC > 2.7V, watchdog output asserted 2
WDO output low voltage VOL 0.4 V ISINK = 6mA, VCC > 4.5V, watchdog output asserted 2
WDO leakage current ILKG 1 µA VWDO = 0 to +5.5V, output deasserted, MAX6369/MAX6371/MAX6373 2
WDO output high voltage VOH 0.8 x VCC ISOURCE = 500µA, VCC > 2.7V, watchdog output deasserted 2
Startup delay period tDELAY 60 180 s All other SET_ conditions 3
Watchdog timeout period tWD 1 3 ms VSET2 = 0V, VSET1 = 0V, VSET0 = 0V 3
Watchdog timeout period tWD 3 9 ms VSET2 = 0V, VSET1 = 0V, SET0 = VCC 3
Watchdog timeout period tWD 10 30 ms VSET2 = 0V, SET1 = VCC, VSET0 = 0V 3
Watchdog timeout period tWD 100 300 ms SET2 = VCC, VSET1 = 0V, VSET0 = 0V 3
Watchdog timeout period tWD 300 900 ms SET2 = VCC, VSET1 = 0V, SET0 = VCC 3
Watchdog timeout period tWD 3 9 s SET2 = VCC, SET1 = VCC, VSET0 = 0V 3
Watchdog timeout period tWD 60 180 s SET2 = VCC, SET1 = VCC, SET0 = VCC 3
Watchdog input pulse width tWDI 100 ns After WDO deasserted 4
Watchdog output pulse width tWDO 100 300 ms MAX6369/MAX6371/MAX6373 4
Internal setup time tSETUP 300 µs After WDO deasserted 4

CAD (KiCad official)

  • Symbol: MAX6371KA+T
  • Footprint: Package_TO_SOT_SMD:SOT-23-8
  • 3D model: SOT-23-8 (KiCad packages3D, STEP)
  • 3D model files: max6371ka-t-etched.step / max6371ka-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max6371ka-t.step / max6371ka-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices Inc Maxim Integrated datasheet (11 pp, sha256 e592e2ff2f316a08, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF