MAX14434FAWE+ from Analog Devices Inc./Maxim Integrated, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDDA	power_in	Side A power supply, 1.71V to 5.5V relative to GNDA, bypass with a 0.1µF ceramic capacitor as close as possible to the pin.
2	GNDA	power_in	Ground reference for Side A.
3	IN1	input	Logic Input 1 on Side A, corresponds to Logic Output 1 on Side B.
4	IN2	input	Logic Input 2 on Side A, corresponds to Logic Output 2 on Side B.
5	IN3	input	Logic Input 3 on Side A, corresponds to Logic Output 3 on Side B.
6	IN4	input	Logic Input 4 on Side A, corresponds to Logic Output 4 on Side B.
7	I.C.	passive	Internally connected; leave unconnected or connect to GNDA or VDDA.
8	GNDA	power_in	Ground reference for Side A.
9	GNDB	power_in	Ground reference for Side B.
10	ENB	input	Active-high enable for Side B, with an internal 5µA pullup to VDDB.
11	OUT4	output	Logic Output 4 on Side B.
12	OUT3	output	Logic Output 3 on Side B.
13	OUT2	output	Logic Output 2 on Side B.
14	OUT1	output	Logic Output 1 on Side B.
15	GNDB	power_in	Ground reference for Side B.
16	VDDB	power_in	Side B power supply, 1.71V to 5.5V relative to GNDB, bypass with a 0.1µF ceramic capacitor as close as possible to the pin.

Key specifications

Parameter	Value
Manufacturer	Analog Devices Inc./Maxim Integrated
Package	SOIC-16
Category	Signal Isolation Devices
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage VDDA	VDDA	1.71		5.5	V	Relative to GNDA	2
Supply Voltage VDDB	VDDB	1.71		5.5	V	Relative to GNDB	2
Undervoltage-Lockout Threshold	VUVLO_	1.5	1.6	1.66	V	VDD_ rising	2
Undervoltage-Lockout Threshold Hysteresis	VUVLO_HYST		45		mV		2
Abs max VDDA to GNDA	VDDA	-0.3		6	V	VDDA to GNDA	2
Abs max VDDB to GNDB	VDDB	-0.3		6	V	VDDB to GNDB	2
Abs max IN_, EN_ Side A		-0.3		6	V	IN_, EN_ on Side A to GNDA	2
Abs max IN_, EN_ Side B		-0.3		6	V	IN_, EN_ on Side B to GNDB	2
Abs max OUT_ Side A		-0.3		0.3	V	OUT_ on Side A to GNDA; max is (VDDA + 0.3V)	2
Abs max OUT_ Side B		-0.3		0.3	V	OUT_ on Side B to GNDB; max is (VDDB + 0.3V)	2
Operating Temperature Range		-40		125	°C		2
Maximum Junction Temperature	TJ			150	°C		2
Storage Temperature Range		-60		150	°C		2
Soldering Temperature (reflow)				260	°C		2
Junction to Ambient Thermal Resistance	θJA		71		°C/W	16 Wide SOIC, four-layer board	2
Junction to Case Thermal Resistance	θJC		24		°C/W	16 Wide SOIC, four-layer board	2
Supply Current IDDA 500kHz	IDDA		0.51	0.93	mA	MAX14434_, 500kHz square wave, CL = 0pF, VDDA = 3.3V	3
Supply Current IDDA 12.5MHz	IDDA		1.59	2.36	mA	MAX14434_, 12.5MHz square wave, CL = 0pF, VDDA = 3.3V	3
Supply Current IDDA 50MHz	IDDA		4.39	6	mA	MAX14434_, 50MHz square wave, CL = 0pF, VDDA = 3.3V	3
Supply Current IDDA 50MHz 5V	IDDA		4.5	6.14	mA	MAX14434_, 50MHz square wave, CL = 0pF, VDDA = 5V	3
Supply Current IDDA 50MHz 1.8V	IDDA		4.21	5.43	mA	MAX14434_, 50MHz square wave, CL = 0pF, VDDA = 1.8V	3
Supply Current IDDB 500kHz	IDDB		0.82	1.41	mA	MAX14434_, 500kHz square wave, CL = 0pF, VDDB = 3.3V	3
Supply Current IDDB 12.5MHz	IDDB		2	2.74	mA	MAX14434_, 12.5MHz square wave, CL = 0pF, VDDB = 3.3V	3
Supply Current IDDB 50MHz	IDDB		5.68	6.88	mA	MAX14434_, 50MHz square wave, CL = 0pF, VDDB = 3.3V	3
Supply Current IDDB 50MHz 5V	IDDB		9.52	11.17	mA	MAX14434_, 50MHz square wave, CL = 0pF, VDDB = 5V	3
Supply Current IDDB 50MHz 1.8V	IDDB		3.46	4.18	mA	MAX14434_, 50MHz square wave, CL = 0pF, VDDB = 1.8V	3
Input High Voltage	VIH	0.7			x VDD_	EN_, IN_, 2.25V ≤ VDD_ ≤ 5.5V	5
Input High Voltage	VIH	0.75			x VDD_	EN_, IN_, 1.71V ≤ VDD_ < 2.25V	5
Input Low Voltage	VIL			0.8	V	EN_, IN_, 2.25V ≤ VDD_ ≤ 5.5V	5
Input Low Voltage	VIL			0.7	V	EN_, IN_, 1.71V ≤ VDD_ < 2.25V	5
Input Hysteresis	VHYS		80		mV	EN_, IN_, MAX1443_C/F/S/V	5
Input Pulldown Current	IPD	1.5	5	10	µA	IN_, MAX1443_E/F/U/V	5
EN Pullup Current	IPU_EN	-10	-5	-1.5	µA	EN_	5
Output Voltage High	VOH	-0.4			V below VDD_	IOUT_ = 4mA source; min is VDD_ - 0.4	5
Output Voltage Low	VOL			0.4	V	IOUT_ = 4mA sink	5
Maximum Data Rate	DRMAX	200			Mbps	2.25V ≤ VDD_ ≤ 5.5V	6
Maximum Data Rate	DRMAX	150			Mbps	1.71V ≤ VDD_ ≤ 1.89V	6
Minimum Pulse Width	PWMIN			5	ns	IN_ to OUT_, 2.25V ≤ VDD_ ≤ 5.5V	6
Minimum Pulse Width	PWMIN			6.67	ns	IN_ to OUT_, 1.71V ≤ VDD_ ≤ 1.89V	6
Propagation Delay tPLH 5V	tPLH	4.1	5.4	9.2	ns	IN_ to OUT_, CL = 15pF, 4.5V ≤ VDD_ ≤ 5.5V	6
Propagation Delay tPLH 3.3V	tPLH	4.2	5.9	10.2	ns	IN_ to OUT_, CL = 15pF, 3.0V ≤ VDD_ ≤ 3.6V	6
Propagation Delay tPLH 2.5V	tPLH	4.9	7.1	13.4	ns	IN_ to OUT_, CL = 15pF, 2.25V ≤ VDD_ ≤ 2.75V	6
Propagation Delay tPLH 1.8V	tPLH	7.1	10.9	20.3	ns	IN_ to OUT_, CL = 15pF, 1.71V ≤ VDD_ ≤ 1.89V	6
Propagation Delay tPHL 5V	tPHL	4.3	5.6	9.4	ns	IN_ to OUT_, CL = 15pF, 4.5V ≤ VDD_ ≤ 5.5V	6
Propagation Delay tPHL 3.3V	tPHL	4.4	6.2	10.5	ns	IN_ to OUT_, CL = 15pF, 3.0V ≤ VDD_ ≤ 3.6V	6
Propagation Delay tPHL 2.5V	tPHL	5.1	7.3	14.1	ns	IN_ to OUT_, CL = 15pF, 2.25V ≤ VDD_ ≤ 2.75V	6
Propagation Delay tPHL 1.8V	tPHL	7.2	10.9	21.7	ns	IN_ to OUT_, CL = 15pF, 1.71V ≤ VDD_ ≤ 1.89V	6
Pulse Width Distortion	PWD		0.3	2	ns	/tPLH - tPHL/	6
Channel-to-Channel Skew (Same Direction) LH	tSCSLH			1.5	ns	1.71V ≤ VDD_ ≤ 5.5V	6
Channel-to-Channel Skew (Same Direction) HL	tSCSHL			1.5	ns	1.71V ≤ VDD_ ≤ 5.5V	6
Part-to-Part Skew tSPLH 3.3V	tSPLH			4.3	ns	3.0V ≤ VDD_ ≤ 3.6V	6
Part-to-Part Skew tSPHL 3.3V	tSPHL			4.7	ns	3.0V ≤ VDD_ ≤ 3.6V	6
ESD Human Body Model, All Pins			4		kV	printed as ±4 kV	9
Maximum Withstand Isolation Voltage	VISO		5000		VRMS	fSW = 60Hz, duration = 60s	11
Maximum Surge Isolation Voltage	VIOSM		10		kV	Basic Insulation, 1.2/50µs pulse per IEC 61000-4-5	11
Common-Mode Transient Immunity	CMTI		50		kV/µs	IN_ = GND_ or VDD_	6
Input Capacitance	CIN		2		pF	IN_, fSW = 1MHz	5

CAD (KiCad official)

Symbol: MAX14434FAWE+
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)
3D model files: max14434fawe-etched.step / max14434fawe-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max14434fawe.step / max14434fawe.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices Inc./Maxim Integrated datasheet (28 pp, sha256 6cda92adf890ee1c, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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MAX14434FAWE+

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