LTC3618IUF#TRPBF

{
  "slug": "ltc3618iuf-trpbf",
  "version": "0.1.0",
  "type": "component",
  "description": "Analog Devices DC-DC Converters, QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "power management (pmic)",
    "ltc3618iuf#trpbf",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "ltc3618iuf-trpbf.kicad_sym",
    "ltc3618iuf-trpbf.kicad_mod",
    "ltc3618iuf-trpbf.glb",
    "ltc3618iuf-trpbf.step",
    "ltc3618iuf-trpbf.lbr",
    "docs/hero.png",
    "docs/ltc3618iuf-trpbf-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "ltc3618iuf-trpbf-hero.glb",
    "ltc3618iuf-trpbf-hero.overlay.json",
    "ltc3618iuf-trpbf-etched.glb"
  ],
  "component": {
    "mpn": "LTC3618IUF#TRPBF",
    "manufacturer": "Analog Devices",
    "package": "QFN-24-EP(4x4)",
    "pin_count": 25,
    "category": "Power Management (PMIC)",
    "subcategory": "DC-DC Converters",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589863894627364864",
    "parts": {
      "symbol": "ltc3618iuf-trpbf.kicad_sym",
      "footprint": "ltc3618iuf-trpbf.kicad_mod",
      "model_3d": "ltc3618iuf-trpbf-hero.glb",
      "model_3d_plain": "ltc3618iuf-trpbf-etched.glb",
      "model_3d_step": "ltc3618iuf-trpbf-etched.step",
      "model_3d_step_plain": "ltc3618iuf-trpbf.step",
      "lbr": "ltc3618iuf-trpbf.lbr"
    },
    "distributor_links": {
      "lcsc": "C685278"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T16:36:30Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VFB1",
        "type": "input",
        "description": "Voltage feedback input for VDDQ that receives the feedback voltage from the external resistive divider across the output."
      },
      {
        "number": "2",
        "name": "ITH1",
        "type": "passive",
        "description": "Error amplifier compensation connection for VDDQ, used for external compensation from ITH to SGND, and tying it to SVIN enables internal compensation."
      },
      {
        "number": "3",
        "name": "MODE/SYNC",
        "type": "input",
        "description": "Mode select: tying to SVIN selects pulse-skipping mode and tying to SGND selects forced continuous mode for VDDQ (VTT is always forced continuous), and a clock applied here synchronizes the switching frequency and forces continuous mode for VDDQ."
      },
      {
        "number": "4",
        "name": "PHASE",
        "type": "input",
        "description": "Phase shift selection between SW1 and SW2: tied to SGND gives 0°, tied to half of SVIN gives 90°, and tied to SVIN gives 180°."
      },
      {
        "number": "5",
        "name": "VFB2",
        "type": "input",
        "description": "Voltage feedback input for VTT, which regulates to VDDQIN × 0.5."
      },
      {
        "number": "6",
        "name": "ITH2",
        "type": "passive",
        "description": "Error amplifier compensation connection for VTT, analogous to ITH1, with the control voltage setting the current comparator threshold."
      },
      {
        "number": "7",
        "name": "VDDQIN",
        "type": "input",
        "description": "External reference input to an internal resistor divider that sets the VTT output so that VFB2 regulates to VDDQIN × 0.5."
      },
      {
        "number": "8",
        "name": "SGND",
        "type": "power_in",
        "description": "Signal ground for all small-signal and compensation components, to be connected to PGND at one point."
      },
      {
        "number": "9",
        "name": "PVIN2",
        "type": "power_in",
        "description": "VTT power supply input, which may connect to a supply equal to or lower than SVIN and is independent of PVIN1."
      },
      {
        "number": "10",
        "name": "PVIN2",
        "type": "power_in",
        "description": "VTT power supply input (second pin of PVIN2), which may connect to a supply equal to or lower than SVIN and is independent of PVIN1."
      },
      {
        "number": "11",
        "name": "SW2",
        "type": "output",
        "description": "VTT switch node that connects to the external inductor and the drains of the internal synchronous power MOSFET switches."
      },
      {
        "number": "12",
        "name": "SW2",
        "type": "output",
        "description": "VTT switch node (second pin of SW2) that connects to the external inductor and the drains of the internal synchronous power MOSFET switches."
      },
      {
        "number": "13",
        "name": "RUN2",
        "type": "input",
        "description": "Enable pin for VTT, which also enables or disables the VTTR buffer output."
      },
      {
        "number": "14",
        "name": "RUN1",
        "type": "input",
        "description": "Enable pin for VDDQ; forcing it above the input threshold enables SW1, and forcing both RUNx pins to ground shuts down the device, which then draws <1µA."
      },
      {
        "number": "15",
        "name": "RT",
        "type": "input",
        "description": "Oscillator frequency setting: a resistor from RT to ground sets the switching frequency, and tying RT to SVIN enables the internal 2.25MHz oscillator."
      },
      {
        "number": "16",
        "name": "PGOOD2",
        "type": "output",
        "description": "Open-drain power good output for VTT."
      },
      {
        "number": "17",
        "name": "VTTR",
        "type": "output",
        "description": "Voltage buffer output equal to VDDQIN × 0.5 with ±10mA output current capability; do not exceed 0.1µF capacitance on this pin."
      },
      {
        "number": "18",
        "name": "PGOOD1",
        "type": "output",
        "description": "Open-drain power good output for VDDQ that is pulled to ground when FB1 is outside the power good window, when RUN1 is disabled, or when an undervoltage is detected at SVIN."
      },
      {
        "number": "19",
        "name": "SW1",
        "type": "output",
        "description": "VDDQ switch node that connects to the external inductor and the drains of the internal synchronous power MOSFET switches."
      },
      {
        "number": "20",
        "name": "SW1",
        "type": "output",
        "description": "VDDQ switch node (second pin of SW1) that connects to the external inductor and the drains of the internal synchronous power MOSFET switches."
      },
      {
        "number": "21",
        "name": "PVIN1",
        "type": "power_in",
        "description": "VDDQ power supply input connected to the source of the internal P-channel power MOSFET, independent of PVIN2 and at equal or lower supply than SVIN."
      },
      {
        "number": "22",
        "name": "PVIN1",
        "type": "power_in",
        "description": "VDDQ power supply input (second pin of PVIN1) connected to the source of the internal P-channel power MOSFET, independent of PVIN2 and at equal or lower supply than SVIN."
      },
      {
        "number": "23",
        "name": "SVIN",
        "type": "power_in",
        "description": "Signal input supply that powers the internal control circuitry and is monitored by the undervoltage lockout comparator, with a VIN operating range of 2.25V to 5.5V."
      },
      {
        "number": "24",
        "name": "TRACK/SS1",
        "type": "input",
        "description": "Internal/external soft-start and external reference input for VDDQ: tying to SVIN selects fixed internal soft-start, while a capacitor to ground and resistor to SVIN set external soft-start timing."
      },
      {
        "number": "25",
        "name": "PGND",
        "type": "power_in",
        "description": "Power ground exposed pad, connected to the sources of the power N-channel MOSFETs, common to both channels, and required to be soldered to the PCB for electrical and rated thermal performance."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The QFN top-view drawing text is scrambled in the extracted datasheet, so the QFN pin numbers were t; Pin 25 is the exposed thermal pad, listed as PGND; the datasheet says it must be soldered to the PCB; KiCad type choices are judgment calls: ITH1/ITH2 are passive compensation nodes, RT is treated as an"
        ],
        "pages_sent": 9,
        "cost_usd": 0.0808,
        "at": "2026-10-18T16:36:14"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589863894627364864",
        "pages": 24,
        "sha256": "3071a7b98ef8f409",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 25,
        "described": 25,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "ltc3618iuf-trpbf.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          4.0,
          4.0,
          0.77
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "096fc110543e6d324c5120c2d38e3dca87a389da9b6fac234f1fe40856295ef4",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ltc3618iuf-trpbf-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          4.0,
          4.0,
          0.77
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "70fa115e31cdcd3bc2b4c734102693662464378e10359ea225fb9c68ad2f6630",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}