component
LTC3226EUD#TRPBF
Public Made by Adomby adom
Analog Devices Battery Management ICs, QFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LTC3226EUD#TRPBF
Analog Devices · Battery Management ICs · QFN-16-EP(3x3)
LTC3226EUD#TRPBF from Analog Devices, in a QFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | power_out | Voltage output that powers the external load from VIN or the supercapacitor via the LDO; it should be bypassed with a low ESR ceramic capacitor of at least 47μF to GND. |
| 2 | PFO | output | Open-drain power-fail status output pulled to ground by an internal N-channel MOSFET when the PFI input is below 1.2V. |
| 3 | PFI | input | Power-fail comparator input with a 1.2V falling threshold and 20mV hysteresis, which controls PFO and the normal/backup operating mode. |
| 4 | LDO_FB | input | LDO feedback compared to the internal 0.8V reference; an external divider between VOUT, LDO_FB and GND programs the LDO output voltage. |
| 5 | GATE | output | External PFET gate drive from the ideal diode controller, which regulates VOUT to 15mV below VIN. |
| 6 | RST_FB | input | Reset comparator input with a 0.74V falling threshold and 20mV hysteresis, controlling the RST output. |
| 7 | RST | output | Open-drain reset status output pulled low when RST_FB falls below 0.74V and released after a 290ms delay once VOUT recovers. |
| 8 | EN_CHG | input | Charge pump enable with an internal pull-up; pulling this pin below 0.4V disables the internal charge pump. |
| 9 | PROG | passive | Charger input current limit programming pin, where a resistor to GND sets the limit with the PROG pin servoed to 1V. |
| 10 | CPO_FB | input | Charge pump feedback compared to the internal 1.2V reference; an external divider between CPO, CPO_FB and GND programs the CPO termination voltage. |
| 11 | CAPGOOD | output | Open-drain CPO status output pulled to ground until CPO is within 7.5% of its target value, then high impedance. |
| 12 | C- | passive | Internal charge pump flying capacitor negative terminal, connected to C+ through a 1μF to 10μF X5R or X7R ceramic capacitor. |
| 13 | VIN | power_in | Primary input supply with a 2.5V to 5.5V input range, bypassed to GND with a low ESR ceramic capacitor of at least 2.2μF. |
| 14 | VMID | passive | Midpoint of the two series supercapacitors, servoed to half of the CPO voltage by a leakage balancer with about 4.5mA source and 5.5mA sink capability. |
| 15 | C+ | passive | Internal charge pump flying capacitor positive terminal, connected to C- through a 1μF to 10μF X5R or X7R ceramic capacitor. |
| 16 | CPO | power_out | Backup supply pin connected to the top plate of the top supercapacitor, which receives power from VIN through the charge pump and supplies VOUT through the LDO during backup. |
| 17 | GND | power_in | Exposed pad ground that must be connected to a continuous ground plane on the second PCB layer through several vias directly under the part. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | QFN-16-EP(3x3) |
| Category | Power Management ICs |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Supply Range | VIN | 2.5 | 5.5 | V | 3 | ||
| VIN Quiescent Current in Normal Mode | IVIN(ST) | 10 | μA | VPFI > 1.2V, VCPO_FB > 1.2V, VIN < VCPO | 3 | ||
| CPO Quiescent Current in Normal Mode | ICPO(ST) | 20 | μA | VPFI > 1.2V, VCPO_FB > 1.2V, VIN < VCPO | 3 | ||
| VOUT Quiescent Current in Normal Mode | IVOUT(ST) | 5 | μA | VOUT = VIN, VPFI > 1.2V, VCPO_FB > 1.2V, VIN < VCPO | 3 | ||
| CPO Quiescent Current in Backup Mode | ICPO(BU) | 24 | μA | VPFI < 1.2V, VLDO_FB > 0.8V, VCPO > VOUT | 3 | ||
| VOUT Quiescent Current in Backup Mode | IVOUT(BU) | 3 | μA | VIN = 0V, VPFI < 1.2V, VLDO_FB > 0.8V, VCPO > VOUT | 3 | ||
| External Ideal Diode Forward Voltage (VIN-VOUT) | VFWD(EDA) | 15 | mV | IVOUT = 2mA | 3 | ||
| Fast Turn-Off Voltage (VIN-VOUT) | VRTO | -45 | mV | VIN Falling | 3 | ||
| Fast Turn-On Voltage (VIN-VOUT) | 45 | mV | VOUT Falling | 3 | |||
| CPO_FB Pin Threshold for Entering Sleep Mode | VCPO_FB | 1.18 | 1.21 | 1.24 | V | 3 | |
| CPO_FB Pin Hysteresis for Exiting Sleep Mode | 20 | mV | 3 | ||||
| Charge Pump FB Pin Input Leakage | ICPO_FB | -50 | 50 | nA | VCPO_FB = 1.3V | 3 | |
| CLK Frequency | fOSC | 0.75 | 0.9 | 1.05 | MHz | 3 | |
| Effective Open-Loop Output Impedance | ROL | 6 | Ω | VCPO = 4.5V, CFLY = 1μF | 3 | ||
| PROG Pin Servo Voltage | VPROG | 0.98 | 1 | 1.02 | V | VCPO_FB < 1.2V | 3 |
| Input Current Limit | IVIN(ILIM) | 360 | mA | RPROG = 33.3k, VCPO = 0V | 3 | ||
| Ratio of VIN Input Current Limit to PROG Pin Current | hPROG | 10500 | A/A | RPROG = 33.3k, VCPO = 0V | 3 | ||
| CPO Pin Charging Current (1x Mode) | ICHRG(1x) | 315 | mA | VIN = 3.8V, RPROG = 33.3k, VCPO = 3V | 3 | ||
| CPO Pin Charging Current (2x Mode) | ICHRG(2x) | 157.5 | mA | RPROG = 33.3k | 3 | ||
| Short-Circuit Charge Current | ISC | 600 | mA | PROG Pin Grounded, VCPO = 0V | 3 | ||
| VIN to CPO Voltage Differential for Switching Mode from 1x to 2x | VMODE | 200 | mV | 3 | |||
| 1x/2x Mode Comparator Hysteresis | 120 | mV | 3 | ||||
| Maximum Voltage Across Either Supercapacitor After Charging | VCLAMP | 2.65 | 2.75 | V | 3 | ||
| Maximum Supercapacitor Stack Voltage | VSTACK | 5.3 | 5.5 | V | 3 | ||
| VMID Output Voltage | VMID | 2.5 | V | 3 | |||
| VMID Current Sourcing Capability | 4.5 | mA | VMID < VCPO/2, VCPO_FB > 1.24V | 3 | |||
| VMID Current Sinking Capability | 5.5 | mA | VMID > VCPO/2, VCPO_FB > 1.24V | 3 | |||
| CPO_FB Pin Threshold Voltage (Rising) for CAPGOOD | 1.09 | 1.11 | 1.13 | V | 3 | ||
| CPO_FB Pin Hysteresis for CAPGOOD | 20 | mV | 3 | ||||
| CAPGOOD Output Low Voltage | 65 | mV | ISINK = 5mA | 3 | |||
| CAPGOOD High Impedance Leakage Current | 1 | μA | VCAPGOOD = 5V | 3 | |||
| LDO FB Servo Voltage | VLDO_FB | 0.76 | 0.8 | 0.82 | V | IVOUT = 1mA | 4 |
| Load Regulation | ΔVLDO_FB/ΔIOUT | 2.7 | mV/A | 1mA < IVOUT < 2A | 4 | ||
| LDO FET RDS(ON) | 200 | mΩ | VCPO = 3.6V | 4 | |||
| LDO_FB Input Leakage Current | ILDO_FB(LEAK) | -60 | 60 | nA | VLDO_FB = 0.9V | 4 | |
| LDO Current Limit | ILIM | 24 | A | 4 | |||
| RST_FB Threshold (Falling Edge) | VRST_FB(TH) | 0.72 | 0.74 | 0.76 | V | 4 | |
| RST_FB Hysteresis | VRST_FB(HYS) | 20 | mV | 4 | |||
| RST_FB Input Leakage Current | IRST_FB(LEAK) | -50 | 50 | nA | VRST_FB = 0.9V | 4 | |
| RST Output Low Voltage | 65 | mV | ISINK = 5mA | 4 | |||
| RST High Impedance Leakage Current | 1 | μA | VRST = 5V | 4 | |||
| RST Delay (RST_FB Rising) | 290 | ms | 4 | ||||
| PFI Input Threshold (Falling Edge) | VPFI(TH) | 1.175 | 1.2 | 1.225 | V | 4 | |
| PFI Input Hysteresis | VPFI(HYS) | 20 | mV | 4 | |||
| PFI Input Leakage Current | IPFI(LEAK) | -50 | 50 | nA | VPFI = 0.5V | 4 | |
| PFO Output Low Voltage | 65 | mV | ISINK = 5mA | 4 | |||
| PFO High Impedance Leakage Current | IPFO(LEAK) | 1 | μA | VPFO = 5V | 4 | ||
| PFI Delay to PFO (PFI Falling) | 0.5 | μs | 4 | ||||
| EN_CHG Input High Voltage | VIH | 1.3 | V | 4 | |||
| EN_CHG Input Low Voltage | VIL | 0.4 | V | 4 | |||
| EN_CHG Input High Current | IIH | -1 | 1 | μA | 4 | ||
| EN_CHG Input Low Current | IIL | -1 | 1 | μA | 4 | ||
| Operating Junction Temperature Range | TJ | -40 | 125 | °C | 2 | ||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 2 | ||
| VIN, VOUT, VMID, CPO, RST, PFO, CAPGOOD, LDO_FB Voltage | -0.3 | 6 | V | 2 | |||
| Thermal Resistance, Junction to Ambient | θJA | 58.7 | °C/W | 2 |
CAD (KiCad official)
- Symbol:
LTC3226EUD#TRPBF - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: QFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
ltc3226eud-trpbf-etched.step/ltc3226eud-trpbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ltc3226eud-trpbf.step/ltc3226eud-trpbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (16 pp, sha256
6096fb27eed897c7, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LTC3226EUD#TRPBF
**Analog Devices** · Battery Management ICs · QFN-16-EP(3x3)
LTC3226EUD#TRPBF from Analog Devices, in a QFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | power_out | Voltage output that powers the external load from VIN or the supercapacitor via the LDO; it should be bypassed with a low ESR ceramic capacitor of at least 47μF to GND. |
| 2 | PFO | output | Open-drain power-fail status output pulled to ground by an internal N-channel MOSFET when the PFI input is below 1.2V. |
| 3 | PFI | input | Power-fail comparator input with a 1.2V falling threshold and 20mV hysteresis, which controls PFO and the normal/backup operating mode. |
| 4 | LDO_FB | input | LDO feedback compared to the internal 0.8V reference; an external divider between VOUT, LDO_FB and GND programs the LDO output voltage. |
| 5 | GATE | output | External PFET gate drive from the ideal diode controller, which regulates VOUT to 15mV below VIN. |
| 6 | RST_FB | input | Reset comparator input with a 0.74V falling threshold and 20mV hysteresis, controlling the RST output. |
| 7 | RST | output | Open-drain reset status output pulled low when RST_FB falls below 0.74V and released after a 290ms delay once VOUT recovers. |
| 8 | EN_CHG | input | Charge pump enable with an internal pull-up; pulling this pin below 0.4V disables the internal charge pump. |
| 9 | PROG | passive | Charger input current limit programming pin, where a resistor to GND sets the limit with the PROG pin servoed to 1V. |
| 10 | CPO_FB | input | Charge pump feedback compared to the internal 1.2V reference; an external divider between CPO, CPO_FB and GND programs the CPO termination voltage. |
| 11 | CAPGOOD | output | Open-drain CPO status output pulled to ground until CPO is within 7.5% of its target value, then high impedance. |
| 12 | C- | passive | Internal charge pump flying capacitor negative terminal, connected to C+ through a 1μF to 10μF X5R or X7R ceramic capacitor. |
| 13 | VIN | power_in | Primary input supply with a 2.5V to 5.5V input range, bypassed to GND with a low ESR ceramic capacitor of at least 2.2μF. |
| 14 | VMID | passive | Midpoint of the two series supercapacitors, servoed to half of the CPO voltage by a leakage balancer with about 4.5mA source and 5.5mA sink capability. |
| 15 | C+ | passive | Internal charge pump flying capacitor positive terminal, connected to C- through a 1μF to 10μF X5R or X7R ceramic capacitor. |
| 16 | CPO | power_out | Backup supply pin connected to the top plate of the top supercapacitor, which receives power from VIN through the charge pump and supplies VOUT through the LDO during backup. |
| 17 | GND | power_in | Exposed pad ground that must be connected to a continuous ground plane on the second PCB layer through several vias directly under the part. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | QFN-16-EP(3x3) |
| Category | Power Management ICs |
| Pins | 17 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Supply Range | VIN | 2.5 | | 5.5 | V | | 3 |
| VIN Quiescent Current in Normal Mode | IVIN(ST) | | | 10 | μA | VPFI > 1.2V, VCPO_FB > 1.2V, VIN < VCPO | 3 |
| CPO Quiescent Current in Normal Mode | ICPO(ST) | | | 20 | μA | VPFI > 1.2V, VCPO_FB > 1.2V, VIN < VCPO | 3 |
| VOUT Quiescent Current in Normal Mode | IVOUT(ST) | | | 5 | μA | VOUT = VIN, VPFI > 1.2V, VCPO_FB > 1.2V, VIN < VCPO | 3 |
| CPO Quiescent Current in Backup Mode | ICPO(BU) | | | 24 | μA | VPFI < 1.2V, VLDO_FB > 0.8V, VCPO > VOUT | 3 |
| VOUT Quiescent Current in Backup Mode | IVOUT(BU) | | | 3 | μA | VIN = 0V, VPFI < 1.2V, VLDO_FB > 0.8V, VCPO > VOUT | 3 |
| External Ideal Diode Forward Voltage (VIN-VOUT) | VFWD(EDA) | | | 15 | mV | IVOUT = 2mA | 3 |
| Fast Turn-Off Voltage (VIN-VOUT) | VRTO | | | -45 | mV | VIN Falling | 3 |
| Fast Turn-On Voltage (VIN-VOUT) | | | | 45 | mV | VOUT Falling | 3 |
| CPO_FB Pin Threshold for Entering Sleep Mode | VCPO_FB | 1.18 | 1.21 | 1.24 | V | | 3 |
| CPO_FB Pin Hysteresis for Exiting Sleep Mode | | | 20 | | mV | | 3 |
| Charge Pump FB Pin Input Leakage | ICPO_FB | -50 | | 50 | nA | VCPO_FB = 1.3V | 3 |
| CLK Frequency | fOSC | 0.75 | 0.9 | 1.05 | MHz | | 3 |
| Effective Open-Loop Output Impedance | ROL | | 6 | | Ω | VCPO = 4.5V, CFLY = 1μF | 3 |
| PROG Pin Servo Voltage | VPROG | 0.98 | 1 | 1.02 | V | VCPO_FB < 1.2V | 3 |
| Input Current Limit | IVIN(ILIM) | | 360 | | mA | RPROG = 33.3k, VCPO = 0V | 3 |
| Ratio of VIN Input Current Limit to PROG Pin Current | hPROG | | 10500 | | A/A | RPROG = 33.3k, VCPO = 0V | 3 |
| CPO Pin Charging Current (1x Mode) | ICHRG(1x) | | 315 | | mA | VIN = 3.8V, RPROG = 33.3k, VCPO = 3V | 3 |
| CPO Pin Charging Current (2x Mode) | ICHRG(2x) | | 157.5 | | mA | RPROG = 33.3k | 3 |
| Short-Circuit Charge Current | ISC | | 600 | | mA | PROG Pin Grounded, VCPO = 0V | 3 |
| VIN to CPO Voltage Differential for Switching Mode from 1x to 2x | VMODE | | 200 | | mV | | 3 |
| 1x/2x Mode Comparator Hysteresis | | | 120 | | mV | | 3 |
| Maximum Voltage Across Either Supercapacitor After Charging | VCLAMP | 2.65 | | 2.75 | V | | 3 |
| Maximum Supercapacitor Stack Voltage | VSTACK | 5.3 | | 5.5 | V | | 3 |
| VMID Output Voltage | VMID | | 2.5 | | V | | 3 |
| VMID Current Sourcing Capability | | | 4.5 | | mA | VMID < VCPO/2, VCPO_FB > 1.24V | 3 |
| VMID Current Sinking Capability | | | 5.5 | | mA | VMID > VCPO/2, VCPO_FB > 1.24V | 3 |
| CPO_FB Pin Threshold Voltage (Rising) for CAPGOOD | | 1.09 | 1.11 | 1.13 | V | | 3 |
| CPO_FB Pin Hysteresis for CAPGOOD | | | 20 | | mV | | 3 |
| CAPGOOD Output Low Voltage | | | | 65 | mV | ISINK = 5mA | 3 |
| CAPGOOD High Impedance Leakage Current | | | | 1 | μA | VCAPGOOD = 5V | 3 |
| LDO FB Servo Voltage | VLDO_FB | 0.76 | 0.8 | 0.82 | V | IVOUT = 1mA | 4 |
| Load Regulation | ΔVLDO_FB/ΔIOUT | | | 2.7 | mV/A | 1mA < IVOUT < 2A | 4 |
| LDO FET RDS(ON) | | | 200 | | mΩ | VCPO = 3.6V | 4 |
| LDO_FB Input Leakage Current | ILDO_FB(LEAK) | -60 | | 60 | nA | VLDO_FB = 0.9V | 4 |
| LDO Current Limit | ILIM | | 24 | | A | | 4 |
| RST_FB Threshold (Falling Edge) | VRST_FB(TH) | 0.72 | 0.74 | 0.76 | V | | 4 |
| RST_FB Hysteresis | VRST_FB(HYS) | | 20 | | mV | | 4 |
| RST_FB Input Leakage Current | IRST_FB(LEAK) | -50 | | 50 | nA | VRST_FB = 0.9V | 4 |
| RST Output Low Voltage | | | | 65 | mV | ISINK = 5mA | 4 |
| RST High Impedance Leakage Current | | | | 1 | μA | VRST = 5V | 4 |
| RST Delay (RST_FB Rising) | | | 290 | | ms | | 4 |
| PFI Input Threshold (Falling Edge) | VPFI(TH) | 1.175 | 1.2 | 1.225 | V | | 4 |
| PFI Input Hysteresis | VPFI(HYS) | | 20 | | mV | | 4 |
| PFI Input Leakage Current | IPFI(LEAK) | -50 | | 50 | nA | VPFI = 0.5V | 4 |
| PFO Output Low Voltage | | | | 65 | mV | ISINK = 5mA | 4 |
| PFO High Impedance Leakage Current | IPFO(LEAK) | | | 1 | μA | VPFO = 5V | 4 |
| PFI Delay to PFO (PFI Falling) | | | 0.5 | | μs | | 4 |
| EN_CHG Input High Voltage | VIH | 1.3 | | | V | | 4 |
| EN_CHG Input Low Voltage | VIL | | | 0.4 | V | | 4 |
| EN_CHG Input High Current | IIH | -1 | | 1 | μA | | 4 |
| EN_CHG Input Low Current | IIL | -1 | | 1 | μA | | 4 |
| Operating Junction Temperature Range | TJ | -40 | | 125 | °C | | 2 |
| Storage Temperature Range | TSTG | -65 | | 150 | °C | | 2 |
| VIN, VOUT, VMID, CPO, RST, PFO, CAPGOOD, LDO_FB Voltage | | -0.3 | | 6 | V | | 2 |
| Thermal Resistance, Junction to Ambient | θJA | | 58.7 | | °C/W | | 2 |
## CAD (KiCad official)
- Symbol: `LTC3226EUD#TRPBF`
- Footprint: `Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`
- 3D model: QFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `ltc3226eud-trpbf-etched.step` / `ltc3226eud-trpbf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ltc3226eud-trpbf.step` / `ltc3226eud-trpbf.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/3226fa.pdf) (16 pp, sha256 `6096fb27eed897c7`, retrieved 2026-11-02, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ltc3226eud-trpbf-datasheet.pdf)