Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

main

Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	13d ago
viewers	ltc2912its8-2-trpbf: viewers · Ray	13d ago
ltc2912its8-2-trpbf-etched.glb	Publish 0.1.0 · Ray	13d ago
ltc2912its8-2-trpbf-etched.step	ltc2912its8-2-trpbf: factory component page (tier=lcsc) · Ray	13d ago
ltc2912its8-2-trpbf-hero.glb	ltc2912its8-2-trpbf: hero GLB from the etched model (keeps the MPN mark) · Ray	13d ago
ltc2912its8-2-trpbf-hero.overlay.json	Publish 0.1.0 · Ray	13d ago
ltc2912its8-2-trpbf.glb	Publish 0.1.0 · Ray	13d ago
ltc2912its8-2-trpbf.kicad_mod	Publish 0.1.0 · Ray	13d ago
ltc2912its8-2-trpbf.kicad_sym	Publish 0.1.0 · Ray	13d ago
ltc2912its8-2-trpbf.lbr	Publish 0.1.0 · Ray	13d ago
ltc2912its8-2-trpbf.step	Publish 0.1.0 · Ray	13d ago
package.json	Publish 0.1.0 · Ray	13d ago
page.json	Set visibility: public · Ray	13d ago
README.md	Publish 0.1.0 · Ray	13d ago

LTC2912ITS8-2#TRPBF

Analog Devices · Supervisor And Reset ICs · TSOT-23-8

LTC2912ITS8-2#TRPBF from Analog Devices, in a TSOT-23-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DIS	input	Output disable input that, when pulled high, keeps the OV and UV pins from asserting except during a UVLO condition, and it has a weak 2µA internal pull-down to GND so it may be left open.
2	UV	output	Undervoltage logic output that asserts low when the VH input is below its 0.5V threshold and is held low for the programmed delay after VH is valid, with a weak pull-up to VCC that may be pulled above VCC by an external pull-up.
3	OV	output	Overvoltage logic output on the LTC2912-2 that asserts low when the VL input is above threshold and is held low for the programmed delay after VL is valid, with a weak pull-up to VCC that may be pulled above VCC by an external pull-up.
4	GND	power_in	Device ground; all voltages are referenced to this pin.
5	TMR	passive	Reset delay timer pin, where an external capacitor of at least 10pF to GND sets a reset delay of 9ms/nF, or tying it to VCC bypasses the timer.
6	VL	input	Voltage Low input that triggers an overvoltage condition when its voltage is above 0.5V, and should be tied to GND if unused.
7	VH	input	Voltage High input that triggers an undervoltage condition when its voltage is below 0.5V, and should be tied to VCC if unused.
8	VCC	power_in	Supply pin that operates as a direct supply up to 6V and as a shunt regulator above 6V, where a series resistor must limit input current to no more than 10mA, and it should be bypassed to GND with 0.1µF or greater.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	TSOT-23-8
Category	Power Management (PMIC)
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VCC Supply Voltage	VCC	2.3			V		4
VCC Shunt Regulator Voltage	VSHUNT	6.2	6.6	7.2	V	ICC = 5mA	4
VCC Shunt Regulator Load Regulation	DVSHUNT		200	300	mV	ICC = 2mA to 10mA	4
Minimum VCC Output Valid	VCCR(MIN)			1	V	DIS = 0V	4
Supply Undervoltage Lockout	VCC(UVLO)	1.9	2	2.1	V	DIS = 0V, VCC Rising	4
Supply Undervoltage Lockout Hysteresis	DVCC(UVHYST)	5	25	50	mV	DIS = 0V	4
Supply Current	ICC		29	70	µA	VCC = 2.3V to 6V	4
Undervoltage/Overvoltage Threshold	VUOT	492	500	508	mV		4
Undervoltage/Overvoltage Threshold to Output Delay	tUOD	50	125	500	µs	VHn = VUOT, 5mV or VLn = VUOT + 5mV	4
VH, VL Input Current	IVHL	-15		15	nA		4
UV/OV Time-Out Period	tUOTO	6	8.5	12.5	ms	CTMR = 1nF	4
OV Latch Clear Input High	VLATCH(VIH)	1.2			V		4
OV Latch Clear Input Low	VLATCH(VIL)			0.8	V		4
LATCH Input Current	ILATCH	-1		1	µA	VLATCH > 0.5V	4
DIS Input Current	IDIS	1	2	3.3	µA	VDIS > 0.5V	4
DIS Input High	VDIS(VIH)	1.2			V		4
DIS Input Low	VDIS(VIL)			0.8	V		4
TMR Pull-Up Current	ITMR(UP)	-1.3	-2.1	-2.8	µA	VTMR = 0V	4
TMR Pull-Down Current	ITMR(DOWN)	1.3	2.1	2.8	µA	VTMR = 1.6V	4
Timer Disable Voltage	VTMR(DIS)	-270		-180	mV	Referenced to VCC	4
Output Voltage High UV/OV/OV	VOH	1			V	VCC = 2.3V, IUV/OV = -1µA	4
Output Voltage Low UV/OV/OV	VOL		0.1	0.3	V	VCC = 2.3V, IUV/OV = 2.5mA	4
Output Voltage Low UV/OV/OV	VOL		0.01	0.15	V	VCC = 1V, IUV = 100µA	4
Operating Temperature Range (LTC2912I)	TA	-40		85	°C	LTC2912I grade	2
Terminal Voltage VCC	VCC	-0.3		6	V		2
Terminal Voltage OV, UV, OV	OV, UV, OV	-0.3		16	V		2
Terminal Voltage TMR	TMR	-0.3			V		2
Terminal Voltage VH, VL, LATCH, DIS	VH, VL, LATCH, DIS	-0.3		7.5	V		2
Terminal Current VCC	IVCC			10	mA		2
Terminal Current UV, OV, OV	IUV, IOV, IOV			10	mA		2
Storage Temperature Range	TSTG	-65		150	°C		2
Maximum Junction Temperature TSOT-23	TJMAX			125	°C	TS8 TSOT-23 package	2
Thermal Resistance Junction-to-Ambient TSOT-23	θJA		195		°C/W	TS8 TSOT-23 package	2

CAD (KiCad official)

Symbol: LTC2912ITS8-2#TRPBF
Footprint: Package_TO_SOT_SMD:TSOT-23-8
3D model: TSOT-23-8 (KiCad packages3D, STEP)
3D model files: ltc2912its8-2-trpbf-etched.step / ltc2912its8-2-trpbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ltc2912its8-2-trpbf.step / ltc2912its8-2-trpbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (14 pp, sha256 b00d264ccc4575ba, retrieved 2026-10-21, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF