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LT8610EMSE#TRPBF

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Analog Devices DC-DC Converters, MSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LT8610EMSE#TRPBF

Analog Devices · DC-DC Converters · MSOP-16-EP

LT8610EMSE#TRPBF from Analog Devices, in a MSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SYNC input External clock synchronization input: ground it for Burst Mode operation at low loads, apply a DC voltage of 3V or higher or tie it to INTVCC for pulse-skipping mode, and do not float it.
2 TR/SS passive Output tracking and soft-start pin: a voltage below 0.97V forces FB to follow TR/SS, an internal 2.2µA pull-up from INTVCC programs the start-up ramp, and an internal 230Ω MOSFET pulls it to ground during shutdown and faults.
3 RT passive A resistor from RT to ground sets the switching frequency, which the datasheet states is adjustable from 200kHz to 2.2MHz.
4 EN/UV input The part is shut down when this pin is low and active when high, with a hysteretic threshold of 1.00V rising and 0.96V falling; tie it to VIN if the shutdown feature is not used.
5 VIN power_in Supplies current to the internal circuitry and the internal top power switch; VIN must be tied together with pin 6, locally bypassed, and VIN is rated to 42V absolute maximum.
6 VIN power_in Supplies current to the internal circuitry and the internal top power switch; it must be tied together with pin 5 and locally bypassed, with VIN rated to 42V absolute maximum.
7 PGND power_in Power switch ground and return path of the internal bottom-side power switch; it must be tied together with pin 8.
8 PGND power_in Power switch ground and return path of the internal bottom-side power switch; it must be tied together with pin 7.
9 SW output Output of the internal power switches; tie SW pins 9, 10 and 11 together and connect them to the inductor and boost capacitor, keeping this node small on the PCB.
10 SW output Output of the internal power switches; tie together with pins 9 and 11 and connect to the inductor and boost capacitor, keeping this node small on the PCB.
11 SW output Output of the internal power switches; tie together with pins 9 and 10 and connect to the inductor and boost capacitor, keeping this node small on the PCB.
12 BST passive Provides the drive voltage for the topside power switch, higher than the input voltage; the 0.1µF boost capacitor must be placed as close as possible to the IC, and the BST pin is rated 4V maximum above the SW pin.
13 INTVCC power_out Internal 3.4V regulator bypass pin that powers the internal drivers and control circuits; maximum output current is 20mA, it must not be loaded externally, and it needs at least a 1µF low ESR ceramic decoupling capacitor to power ground placed close to the IC.
14 BIAS power_in Supplies the internal regulator from BIAS instead of VIN when tied above 3.1V; for output voltages of 3.3V and above it should be tied to VOUT, and a different supply needs a 1µF local bypass capacitor, with BIAS rated 30V absolute maximum.
15 PG output Open-drain power-good output that stays low until FB is within ±9% of the regulation voltage with no fault conditions, and is valid when VIN is above 3.4V regardless of the EN/UV state; the PG pin is rated 42V absolute maximum.
16 FB input Feedback input that the LT8610 regulates to 0.970V, connected to the feedback resistor divider tap, with a phase lead capacitor (typically 4.7pF to 10pF) connected between FB and VOUT.
17 GND power_in Exposed pad ground that must be connected to the negative terminal of the input capacitor and soldered to the PCB to lower thermal resistance.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package MSOP-16-EP
Category Power Management (PMIC)
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Minimum Input Voltage 2.9 3.4 V l (full operating temperature range) 2
VIN Quiescent Current 1 3 µA VEN/UV = 0V, VSYNC = 0V 2
VIN Quiescent Current 1 8 µA l (full operating temperature range); VEN/UV = 0V, VSYNC = 0V 2
VIN Quiescent Current 1.7 4 µA VEN/UV = 2V, Not Switching, VSYNC = 0V 2
VIN Quiescent Current 1.7 10 µA l (full operating temperature range); VEN/UV = 2V, Not Switching, VSYNC = 0V 2
VIN Quiescent Current 0.24 0.5 mA VEN/UV = 2V, Not Switching, VSYNC = 2V 2
VIN Current in Regulation 24 50 µA l (full operating temperature range); VOUT = 0.97V, VIN = 6V, Output Load = 100µA 2
VIN Current in Regulation 210 350 µA l (full operating temperature range); VOUT = 0.97V, VIN = 6V, Output Load = 1mA 2
Feedback Reference Voltage 0.964 0.97 0.976 V VIN = 6V, ILOAD = 0.5A 2
Feedback Reference Voltage 0.958 0.97 0.982 V l (full operating temperature range); VIN = 6V, ILOAD = 0.5A 2
Feedback Voltage Line Regulation 0.004 0.02 %/V l (full operating temperature range); VIN = 4.0V to 42V, ILOAD = 0.5A 2
Feedback Pin Input Current -20 20 nA VFB = 1V 2
INTVCC Voltage 3.23 3.4 3.57 V ILOAD = 0mA, VBIAS = 0V 2
INTVCC Voltage 3.25 3.29 3.35 V ILOAD = 0mA, VBIAS = 3.3V 2
INTVCC Undervoltage Lockout 2.5 2.6 2.7 V 2
Minimum On-Time 30 50 70 ns l (full operating temperature range); ILOAD = 1A, SYNC = 0V 2
Minimum On-Time 30 45 65 ns l (full operating temperature range); ILOAD = 1A, SYNC = 3.3V 2
Minimum Off-Time 50 80 110 ns 2
Oscillator Frequency 180 210 240 kHz l (full operating temperature range); RT = 221k, ILOAD = 1A 3
Oscillator Frequency 665 700 735 kHz l (full operating temperature range); RT = 60.4k, ILOAD = 1A 3
Oscillator Frequency 1.85 2 2.15 MHz l (full operating temperature range); RT = 18.2k, ILOAD = 1A 3
Top Power NMOS Current Limit 3.5 4.8 5.8 A l (full operating temperature range) 3
Bottom Power NMOS Current Limit 2.5 3.3 4.8 A VINTVCC = 3.4V 3
SW Leakage Current -1.5 1.5 µA VIN = 42V, VSW = 0V, 42V 3
EN/UV Pin Threshold 0.94 1 1.06 V EN/UV Rising; l (full operating temperature range) 3
EN/UV Pin Current -20 20 nA VEN/UV = 2V 3
PG Upper Threshold Offset from VFB 6 9 12 % VFB Falling; l (full operating temperature range) 3
PG Lower Threshold Offset from VFB -12 -9 -6 % VFB Rising; l (full operating temperature range) 3
PG Leakage -40 40 nA VPG = 3.3V 3
PG Pull-Down Resistance 680 2000 Ω l (full operating temperature range); VPG = 0.1V 3
SYNC Threshold (SYNC Falling) 0.8 1.1 1.4 V SYNC Falling 3
SYNC Threshold (SYNC Rising) 1.6 2 2.4 V SYNC Rising 3
SYNC Pin Current -40 40 nA VSYNC = 2V 3
TR/SS Source Current 1.2 2.2 3.2 µA l (full operating temperature range) 3
VIN, EN/UV, PG Voltage 42 V 2
BIAS Voltage 30 V 2
BST Pin Above SW Pin 4 V 2
FB, TR/SS, RT, INTVCC Voltage 4 V 2
SYNC Voltage 6 V 2
Storage Temperature Range -65 150 °C 2
Operating Junction Temperature Range (LT8610E) -40 125 °C LT8610E (Note 2) 2
INTVCC Maximum Output Current 20 mA 8
SYNC DC Voltage for Pulse-Skipping Mode 3 V Apply DC voltage of 3V or higher, or tie to INTVCC 8
Thermal Resistance Junction-to-Ambient θJA 40 °C/W 2
Thermal Resistance Junction-to-Case (Exposed Pad) θJC(PAD) 10 °C/W 2

CAD (KiCad official)

  • Symbol: LT8610EMSE#TRPBF
  • Footprint: Package_SO:MSOP-16-1EP_3x4.039mm_P0.5mm_EP1.651x2.845mm
  • 3D model: MSOP-16-EP (KiCad packages3D, STEP)
  • 3D model files: lt8610emse-trpbf-etched.step / lt8610emse-trpbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt8610emse-trpbf.step / lt8610emse-trpbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (22 pp, sha256 142ed1a2842742ea, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF