component
LT8582EDKD#PBF
Public Made by Adomby adom
Analog Devices DC-DC Converters, DFN-24-EP(4x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LT8582EDKD#PBF
Analog Devices · DC-DC Converters · DFN-24-EP(4x7)
LT8582EDKD#PBF from Analog Devices, in a DFN-24-EP(4x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SWA1 | output | Master switch collector pin for channel 1, designed to handle a peak collector current of 1.7A (minimum), so keep the metal trace area connected to it small to reduce EMI. |
| 2 | VIN1 | power_in | Input supply pin for channel 1 that must be locally bypassed. |
| 3 | PG1 | output | Active-high open-drain power good output for channel 1 that is valid only when SHDN > 1.31V and VIN > 2.3V and requires a pull-up resistor; it indicates VFBX is within 4% of regulation (VFBX > 1.15V noninverting, VFBX < 65mV inverting). |
| 4 | GATE1 | output | PMOS gate drive pin for channel 1 that acts as a pull-down current source for output short-circuit protection or output disconnect, with a maximum pull-down current of 1mA at SS voltages above 550mV. |
| 5 | VC1 | passive | Error amplifier output for channel 1 to which the external compensation network is tied. |
| 6 | FBX1 | input | Positive and negative feedback pin for channel 1, connected to VOUT through a resistor set by the 1.204V feedback voltage and 83.3µA FBX bias current equations for noninverting or inverting converters. |
| 7 | FBX2 | input | Positive and negative feedback pin for channel 2, connected to VOUT through a resistor set by the 1.204V feedback voltage and 83.3µA FBX bias current equations for noninverting or inverting converters. |
| 8 | VC2 | passive | Error amplifier output for channel 2 to which the external compensation network is tied. |
| 9 | GATE2 | output | PMOS gate drive pin for channel 2 that acts as a pull-down current source for output short-circuit protection or output disconnect, with a maximum pull-down current of 1mA at SS voltages above 550mV. |
| 10 | PG2 | output | Active-high open-drain power good output for channel 2 that is valid only when SHDN > 1.31V and VIN > 2.3V and requires a pull-up resistor; it indicates VFBX is within 4% of regulation (VFBX > 1.15V noninverting, VFBX < 65mV inverting). |
| 11 | VIN2 | power_in | Input supply pin for channel 2 that must be locally bypassed. |
| 12 | SWA2 | output | Master switch collector pin for channel 2, designed to handle a peak collector current of 1.7A (minimum), so keep the metal trace area connected to it small to reduce EMI. |
| 13 | SWB2 | output | Slave switch collector pin for channel 2, designed to handle a peak collector current of 1.3A (minimum), so keep the metal trace area connected to it small to reduce EMI. |
| 14 | CLKOUT2 | output | Clock output for channel 2 that is in phase with the internal oscillator or SYNC pin, with a duty cycle that varies with junction temperature, and is only meant to drive capacitive loads up to 120pF. |
| 15 | SHDN2 | input | Shutdown pin for channel 2 that must be driven below 0.3V to disable the channel and above 1.31V (typical) to activate it and restart soft-start, and must not be floated. |
| 16 | RT2 | passive | Timing resistor pin for channel 2 where a resistor to ground sets the fixed free-running switching frequency, and the pin must not be floated. |
| 17 | SS2 | passive | Soft-start pin for channel 2 where a soft-start capacitor is placed; at start-up it is charged by a nominal 250k resistor to about 2.1V. |
| 18 | SYNC2 | input | Synchronization input for channel 2 where the clock high level must exceed 1.3V and the low level must be below 0.4V; driving it below 0.4V reverts channel 2 to its internal free-running clock. |
| 19 | SYNC1 | input | Synchronization input for channel 1 where the clock high level must exceed 1.3V and the low level must be below 0.4V; driving it below 0.4V reverts channel 1 to its internal free-running clock. |
| 20 | SS1 | passive | Soft-start pin for channel 1 where a soft-start capacitor is placed; at start-up it is charged by a nominal 250k resistor to about 2.1V. |
| 21 | RT1 | passive | Timing resistor pin for channel 1 where a resistor to ground sets the fixed free-running switching frequency, and the pin must not be floated. |
| 22 | SHDN1 | input | Shutdown pin for channel 1 that must be driven below 0.3V to disable the channel and above 1.31V (typical) to activate it and restart soft-start, and must not be floated. |
| 23 | CLKOUT1 | output | Clock output for channel 1 that is 180° out of phase with the internal oscillator or SYNC pin with a fixed ~50% duty cycle, and is only meant to drive capacitive loads up to 120pF. |
| 24 | SWB1 | output | Slave switch collector pin for channel 1, designed to handle a peak collector current of 1.3A (minimum), so keep the metal trace area connected to it small to reduce EMI. |
| 25 | GND | power_in | Ground exposed pad that must be soldered directly to the local ground plane. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | DFN-24-EP(4x7) |
| Category | Power Management ICs |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN1 Voltage | -0.3 | 40 | V | 2 | |||
| SWA1/SWB1 Voltage | -0.4 | 42 | V | 2 | |||
| RT1 Voltage | -0.3 | 5 | V | 2 | |||
| SS1 Voltage | -0.3 | 2.5 | V | 2 | |||
| FBX1 Voltage | -0.3 | 5 | V | 2 | |||
| VC1 Voltage | -0.3 | 2 | V | 2 | |||
| SHDN1 Voltage | 40 | V | 2 | ||||
| SHDN1 Current | -1 | mA | 2 | ||||
| SYNC1 Voltage | -0.3 | 5.5 | V | 2 | |||
| GATE1 Voltage | -0.3 | 60 | V | 2 | |||
| PG1 Voltage | -0.3 | 40 | V | 2 | |||
| PG1 Current | -0.5 | 0.5 | mA | ±0.5mA as printed | 2 | ||
| Storage Temperature Range | -65 | 150 | °C | 2 | |||
| Operating Junction Temperature Range | -40 | 125 | °C | LT8582E | 2 | ||
| Wide Input Range (Operating) | VIN | 2.5 | 22 | V | Operating; 40V maximum transient (Features) | 1 | |
| Maximum Junction Temperature (TJMAX) | TJMAX | 125 | °C | 2 | |||
| Minimum Input Voltage | VIN | 2.3 | 2.5 | V | 3 | ||
| VIN Overvoltage Lockout | 22.2 | 24.5 | 27 | V | 3 | ||
| Positive Feedback Voltage | 1.185 | 1.204 | 1.22 | V | 3 | ||
| Negative Feedback Voltage | 2 | 7 | 16 | mV | 3 | ||
| Positive FBX Pin Bias Current | 81 | 83.3 | 85 | μA | VFBX = Positive Feedback Voltage, Current into Pin | 3 | |
| Negative FBX Pin Bias Current | 81 | 83.3 | 85.5 | μA | VFBX = Negative Feedback Voltage, Current out of Pin | 3 | |
| Quiescent Current | 2.1 | 2.5 | mA | VSHDN = 2.5V, Not Switching | 3 | ||
| Quiescent Current in Shutdown | 0 | 1 | μA | VSHDN = 0 | 3 | ||
| Reference Line Regulation | 0.01 | 0.05 | %/V | 2.5V ≤ VIN ≤ 20V | 3 | ||
| Switching Frequency | fOSC | 2.125 | 2.5 | 2.875 | MHz | RT = 31.6kΩ | 3 |
| Switching Frequency | fOSC | 170 | 200 | 230 | kHz | RT = 407kΩ | 3 |
| Switching Frequency Range | 200 | 2500 | kHz | Free-Running or Synchronizing | 3 | ||
| SYNC High Level for Sync | 1.3 | V | 3 | ||||
| SYNC Low Level for Sync | 0.4 | V | 3 | ||||
| SYNC Clock Pulse Duty Cycle | 20 | 80 | % | VSYNC = 0V to 2V | 3 | ||
| SWA Current Limit | 1.8 | 2.4 | 3 | A | Minimum Duty Cycle | 3 | |
| SWA Current Limit | 1.3 | 1.8 | 2.5 | A | Maximum Duty Cycle | 3 | |
| SWA FAULT Current Limit | 2.2 | 2.8 | 3.5 | A | Minimum Duty Cycle | 3 | |
| SWA FAULT Current Limit | 1.6 | 2.3 | 3 | A | Maximum Duty Cycle | 3 | |
| SWA + SWB Current Limit | 3.3 | 4.3 | 5.4 | A | Minimum Duty Cycle, ISWB/ISWA = 0.79 | 3 | |
| SWA + SWB Current Limit | 2.3 | 4.1 | 4.5 | A | Maximum Duty Cycle, ISWB/ISWA = 0.79 | 3 | |
| SWA + SWB FAULT Current Limit | 4 | 5 | 6.3 | A | Minimum Duty Cycle, ISWB/ISWA = 0.79 | 3 | |
| SWA + SWB FAULT Current Limit | 2.8 | 4 | 5.4 | A | Maximum Duty Cycle, ISWB/ISWA = 0.79 | 3 | |
| SS Charge Current | 5.7 | 8.8 | 11.7 | μA | VSS = 30mV, Current Flows out of SS Pin | 3 | |
| SS Discharge Current | 5.7 | 8.8 | 11.7 | μA | Part in FAULT, VSS = 2.1V, Current Flows into SS Pin | 3 | |
| SS High Detection Voltage | 1.65 | 1.84 | 2 | V | Part in FAULT | 3 | |
| SS Low Detection Voltage | 15 | 55 | 100 | mV | Part Exiting FAULT | 3 | |
| SHDN Minimum Input Voltage High | 1.26 | 1.31 | 1.4 | V | Active Mode, SHDN Rising | 3 | |
| SHDN Minimum Input Voltage High | 1.21 | 1.27 | 1.35 | V | Active Mode, SHDN Falling | 3 | |
| SHDN Input Voltage Low | 0.3 | V | Shutdown Mode | 3 | |||
| SHDN Pin Bias Current | 10.1 | 12.1 | 14.1 | μA | VSHDN = 3V | 4 | |
| SHDN Pin Bias Current | 45 | 65 | μA | VSHDN = 1.3V | 4 | ||
| SHDN Pin Bias Current | 0 | 0.1 | μA | VSHDN = 0V | 4 | ||
| CLKOUT Output Voltage High | 1.9 | 2.1 | 2.3 | V | 1mA out of CLKOUT Pin | 4 | |
| CLKOUT Output Voltage Low | 30 | 200 | mV | 1mA into CLKOUT Pin | 4 | ||
| GATE Pull-Down Current | 0.8 | 1 | 1.2 | mA | VGATE = 3V | 4 | |
| SWA Leakage Current | 0.01 | 1 | μA | VSWA = 5V, VSHDN = 0 | 3 | ||
| SWB Leakage Current | 0.01 | 1 | μA | VSWB = 5V, VSHDN = 0 | 3 | ||
| PG Threshold for Positive Feedback Voltage | 1.09 | 1.15 | 1.2 | V | VFBX Rising | 4 | |
| PG Threshold for Negative Feedback Voltage | 20 | 65 | 120 | mV | VFBX Falling | 4 | |
| PG Output Voltage Low | 70 | 150 | mV | 100μA into PG Pin, VFBX = 1V | 4 | ||
| Thermal Resistance, Junction to Ambient | θJA | 34 | °C/W | 2 | |||
| Thermal Resistance, Junction to Case | θJC | 7 | °C/W | 2 |
CAD (KiCad official)
- Symbol:
LT8582EDKD#PBF - Footprint:
Package_DFN_QFN:DFN-24-1EP_4x7mm_P0.5mm_EP2.64x6.44mm - 3D model: DFN-24-EP(4x7) (KiCad packages3D, STEP)
- 3D model files:
lt8582edkd-pbf-etched.step/lt8582edkd-pbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lt8582edkd-pbf.step/lt8582edkd-pbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (36 pp, sha256
d4cd3a1bf42e8ed8, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LT8582EDKD#PBF
**Analog Devices** · DC-DC Converters · DFN-24-EP(4x7)
LT8582EDKD#PBF from Analog Devices, in a DFN-24-EP(4x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SWA1 | output | Master switch collector pin for channel 1, designed to handle a peak collector current of 1.7A (minimum), so keep the metal trace area connected to it small to reduce EMI. |
| 2 | VIN1 | power_in | Input supply pin for channel 1 that must be locally bypassed. |
| 3 | PG1 | output | Active-high open-drain power good output for channel 1 that is valid only when SHDN > 1.31V and VIN > 2.3V and requires a pull-up resistor; it indicates VFBX is within 4% of regulation (VFBX > 1.15V noninverting, VFBX < 65mV inverting). |
| 4 | GATE1 | output | PMOS gate drive pin for channel 1 that acts as a pull-down current source for output short-circuit protection or output disconnect, with a maximum pull-down current of 1mA at SS voltages above 550mV. |
| 5 | VC1 | passive | Error amplifier output for channel 1 to which the external compensation network is tied. |
| 6 | FBX1 | input | Positive and negative feedback pin for channel 1, connected to VOUT through a resistor set by the 1.204V feedback voltage and 83.3µA FBX bias current equations for noninverting or inverting converters. |
| 7 | FBX2 | input | Positive and negative feedback pin for channel 2, connected to VOUT through a resistor set by the 1.204V feedback voltage and 83.3µA FBX bias current equations for noninverting or inverting converters. |
| 8 | VC2 | passive | Error amplifier output for channel 2 to which the external compensation network is tied. |
| 9 | GATE2 | output | PMOS gate drive pin for channel 2 that acts as a pull-down current source for output short-circuit protection or output disconnect, with a maximum pull-down current of 1mA at SS voltages above 550mV. |
| 10 | PG2 | output | Active-high open-drain power good output for channel 2 that is valid only when SHDN > 1.31V and VIN > 2.3V and requires a pull-up resistor; it indicates VFBX is within 4% of regulation (VFBX > 1.15V noninverting, VFBX < 65mV inverting). |
| 11 | VIN2 | power_in | Input supply pin for channel 2 that must be locally bypassed. |
| 12 | SWA2 | output | Master switch collector pin for channel 2, designed to handle a peak collector current of 1.7A (minimum), so keep the metal trace area connected to it small to reduce EMI. |
| 13 | SWB2 | output | Slave switch collector pin for channel 2, designed to handle a peak collector current of 1.3A (minimum), so keep the metal trace area connected to it small to reduce EMI. |
| 14 | CLKOUT2 | output | Clock output for channel 2 that is in phase with the internal oscillator or SYNC pin, with a duty cycle that varies with junction temperature, and is only meant to drive capacitive loads up to 120pF. |
| 15 | SHDN2 | input | Shutdown pin for channel 2 that must be driven below 0.3V to disable the channel and above 1.31V (typical) to activate it and restart soft-start, and must not be floated. |
| 16 | RT2 | passive | Timing resistor pin for channel 2 where a resistor to ground sets the fixed free-running switching frequency, and the pin must not be floated. |
| 17 | SS2 | passive | Soft-start pin for channel 2 where a soft-start capacitor is placed; at start-up it is charged by a nominal 250k resistor to about 2.1V. |
| 18 | SYNC2 | input | Synchronization input for channel 2 where the clock high level must exceed 1.3V and the low level must be below 0.4V; driving it below 0.4V reverts channel 2 to its internal free-running clock. |
| 19 | SYNC1 | input | Synchronization input for channel 1 where the clock high level must exceed 1.3V and the low level must be below 0.4V; driving it below 0.4V reverts channel 1 to its internal free-running clock. |
| 20 | SS1 | passive | Soft-start pin for channel 1 where a soft-start capacitor is placed; at start-up it is charged by a nominal 250k resistor to about 2.1V. |
| 21 | RT1 | passive | Timing resistor pin for channel 1 where a resistor to ground sets the fixed free-running switching frequency, and the pin must not be floated. |
| 22 | SHDN1 | input | Shutdown pin for channel 1 that must be driven below 0.3V to disable the channel and above 1.31V (typical) to activate it and restart soft-start, and must not be floated. |
| 23 | CLKOUT1 | output | Clock output for channel 1 that is 180° out of phase with the internal oscillator or SYNC pin with a fixed ~50% duty cycle, and is only meant to drive capacitive loads up to 120pF. |
| 24 | SWB1 | output | Slave switch collector pin for channel 1, designed to handle a peak collector current of 1.3A (minimum), so keep the metal trace area connected to it small to reduce EMI. |
| 25 | GND | power_in | Ground exposed pad that must be soldered directly to the local ground plane. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | DFN-24-EP(4x7) |
| Category | Power Management ICs |
| Pins | 25 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN1 Voltage | | -0.3 | | 40 | V | | 2 |
| SWA1/SWB1 Voltage | | -0.4 | | 42 | V | | 2 |
| RT1 Voltage | | -0.3 | | 5 | V | | 2 |
| SS1 Voltage | | -0.3 | | 2.5 | V | | 2 |
| FBX1 Voltage | | -0.3 | | 5 | V | | 2 |
| VC1 Voltage | | -0.3 | | 2 | V | | 2 |
| SHDN1 Voltage | | | | 40 | V | | 2 |
| SHDN1 Current | | -1 | | | mA | | 2 |
| SYNC1 Voltage | | -0.3 | | 5.5 | V | | 2 |
| GATE1 Voltage | | -0.3 | | 60 | V | | 2 |
| PG1 Voltage | | -0.3 | | 40 | V | | 2 |
| PG1 Current | | -0.5 | | 0.5 | mA | ±0.5mA as printed | 2 |
| Storage Temperature Range | | -65 | | 150 | °C | | 2 |
| Operating Junction Temperature Range | | -40 | | 125 | °C | LT8582E | 2 |
| Wide Input Range (Operating) | VIN | 2.5 | | 22 | V | Operating; 40V maximum transient (Features) | 1 |
| Maximum Junction Temperature (TJMAX) | TJMAX | | | 125 | °C | | 2 |
| Minimum Input Voltage | VIN | | 2.3 | 2.5 | V | | 3 |
| VIN Overvoltage Lockout | | 22.2 | 24.5 | 27 | V | | 3 |
| Positive Feedback Voltage | | 1.185 | 1.204 | 1.22 | V | | 3 |
| Negative Feedback Voltage | | 2 | 7 | 16 | mV | | 3 |
| Positive FBX Pin Bias Current | | 81 | 83.3 | 85 | μA | VFBX = Positive Feedback Voltage, Current into Pin | 3 |
| Negative FBX Pin Bias Current | | 81 | 83.3 | 85.5 | μA | VFBX = Negative Feedback Voltage, Current out of Pin | 3 |
| Quiescent Current | | | 2.1 | 2.5 | mA | VSHDN = 2.5V, Not Switching | 3 |
| Quiescent Current in Shutdown | | | 0 | 1 | μA | VSHDN = 0 | 3 |
| Reference Line Regulation | | | 0.01 | 0.05 | %/V | 2.5V ≤ VIN ≤ 20V | 3 |
| Switching Frequency | fOSC | 2.125 | 2.5 | 2.875 | MHz | RT = 31.6kΩ | 3 |
| Switching Frequency | fOSC | 170 | 200 | 230 | kHz | RT = 407kΩ | 3 |
| Switching Frequency Range | | 200 | | 2500 | kHz | Free-Running or Synchronizing | 3 |
| SYNC High Level for Sync | | 1.3 | | | V | | 3 |
| SYNC Low Level for Sync | | | | 0.4 | V | | 3 |
| SYNC Clock Pulse Duty Cycle | | 20 | | 80 | % | VSYNC = 0V to 2V | 3 |
| SWA Current Limit | | 1.8 | 2.4 | 3 | A | Minimum Duty Cycle | 3 |
| SWA Current Limit | | 1.3 | 1.8 | 2.5 | A | Maximum Duty Cycle | 3 |
| SWA FAULT Current Limit | | 2.2 | 2.8 | 3.5 | A | Minimum Duty Cycle | 3 |
| SWA FAULT Current Limit | | 1.6 | 2.3 | 3 | A | Maximum Duty Cycle | 3 |
| SWA + SWB Current Limit | | 3.3 | 4.3 | 5.4 | A | Minimum Duty Cycle, ISWB/ISWA = 0.79 | 3 |
| SWA + SWB Current Limit | | 2.3 | 4.1 | 4.5 | A | Maximum Duty Cycle, ISWB/ISWA = 0.79 | 3 |
| SWA + SWB FAULT Current Limit | | 4 | 5 | 6.3 | A | Minimum Duty Cycle, ISWB/ISWA = 0.79 | 3 |
| SWA + SWB FAULT Current Limit | | 2.8 | 4 | 5.4 | A | Maximum Duty Cycle, ISWB/ISWA = 0.79 | 3 |
| SS Charge Current | | 5.7 | 8.8 | 11.7 | μA | VSS = 30mV, Current Flows out of SS Pin | 3 |
| SS Discharge Current | | 5.7 | 8.8 | 11.7 | μA | Part in FAULT, VSS = 2.1V, Current Flows into SS Pin | 3 |
| SS High Detection Voltage | | 1.65 | 1.84 | 2 | V | Part in FAULT | 3 |
| SS Low Detection Voltage | | 15 | 55 | 100 | mV | Part Exiting FAULT | 3 |
| SHDN Minimum Input Voltage High | | 1.26 | 1.31 | 1.4 | V | Active Mode, SHDN Rising | 3 |
| SHDN Minimum Input Voltage High | | 1.21 | 1.27 | 1.35 | V | Active Mode, SHDN Falling | 3 |
| SHDN Input Voltage Low | | | | 0.3 | V | Shutdown Mode | 3 |
| SHDN Pin Bias Current | | 10.1 | 12.1 | 14.1 | μA | VSHDN = 3V | 4 |
| SHDN Pin Bias Current | | | 45 | 65 | μA | VSHDN = 1.3V | 4 |
| SHDN Pin Bias Current | | | 0 | 0.1 | μA | VSHDN = 0V | 4 |
| CLKOUT Output Voltage High | | 1.9 | 2.1 | 2.3 | V | 1mA out of CLKOUT Pin | 4 |
| CLKOUT Output Voltage Low | | | 30 | 200 | mV | 1mA into CLKOUT Pin | 4 |
| GATE Pull-Down Current | | 0.8 | 1 | 1.2 | mA | VGATE = 3V | 4 |
| SWA Leakage Current | | | 0.01 | 1 | μA | VSWA = 5V, VSHDN = 0 | 3 |
| SWB Leakage Current | | | 0.01 | 1 | μA | VSWB = 5V, VSHDN = 0 | 3 |
| PG Threshold for Positive Feedback Voltage | | 1.09 | 1.15 | 1.2 | V | VFBX Rising | 4 |
| PG Threshold for Negative Feedback Voltage | | 20 | 65 | 120 | mV | VFBX Falling | 4 |
| PG Output Voltage Low | | | 70 | 150 | mV | 100μA into PG Pin, VFBX = 1V | 4 |
| Thermal Resistance, Junction to Ambient | θJA | | 34 | | °C/W | | 2 |
| Thermal Resistance, Junction to Case | θJC | | 7 | | °C/W | | 2 |
## CAD (KiCad official)
- Symbol: `LT8582EDKD#PBF`
- Footprint: `Package_DFN_QFN:DFN-24-1EP_4x7mm_P0.5mm_EP2.64x6.44mm`
- 3D model: DFN-24-EP(4x7) (KiCad packages3D, STEP)
- 3D model files: `lt8582edkd-pbf-etched.step` / `lt8582edkd-pbf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lt8582edkd-pbf.step` / `lt8582edkd-pbf.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/8582f.pdf) (36 pp, sha256 `d4cd3a1bf42e8ed8`, retrieved 2026-10-28, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/lt8582edkd-pbf-datasheet.pdf)