component
LT8582EDKD#PBF
Public Made by Adomby adom
Analog Devices DC-DC Converters, DFN-24-EP(4x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.md+127docs/hero.pngdocs/lt8582edkd-pbf-datasheet.pdflt8582edkd-pbf-etched.glblt8582edkd-pbf-hero.glblt8582edkd-pbf-hero.overlay.json+625lt8582edkd-pbf.glblt8582edkd-pbf.kicad_mod+413lt8582edkd-pbf.kicad_sym+113lt8582edkd-pbf.lbr+187lt8582edkd-pbf.step+6403package.json+337page.json+343viewers/footprint.html+1viewers/symbol.html+1README.mdadded+127@@ -0,0 +1,127 @@+# LT8582EDKD#PBF++**Analog Devices** · DC-DC Converters · DFN-24-EP(4x7)++LT8582EDKD#PBF from Analog Devices, in a DFN-24-EP(4x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | SWA1 | output | Master switch collector pin for channel 1, designed to handle a peak collector current of 1.7A (minimum), so keep the metal trace area connected to it small to reduce EMI. |+| 2 | VIN1 | power_in | Input supply pin for channel 1 that must be locally bypassed. |+| 3 | PG1 | output | Active-high open-drain power good output for channel 1 that is valid only when SHDN > 1.31V and VIN > 2.3V and requires a pull-up resistor; it indicates VFBX is within 4% of regulation (VFBX > 1.15V noninverting, VFBX < 65mV inverting). |+| 4 | GATE1 | output | PMOS gate drive pin for channel 1 that acts as a pull-down current source for output short-circuit protection or output disconnect, with a maximum pull-down current of 1mA at SS voltages above 550mV. |+| 5 | VC1 | passive | Error amplifier output for channel 1 to which the external compensation network is tied. |+| 6 | FBX1 | input | Positive and negative feedback pin for channel 1, connected to VOUT through a resistor set by the 1.204V feedback voltage and 83.3µA FBX bias current equations for noninverting or inverting converters. |+| 7 | FBX2 | input | Positive and negative feedback pin for channel 2, connected to VOUT through a resistor set by the 1.204V feedback voltage and 83.3µA FBX bias current equations for noninverting or inverting converters. |+| 8 | VC2 | passive | Error amplifier output for channel 2 to which the external compensation network is tied. |+| 9 | GATE2 | output | PMOS gate drive pin for channel 2 that acts as a pull-down current source for output short-circuit protection or output disconnect, with a maximum pull-down current of 1mA at SS voltages above 550mV. |+| 10 | PG2 | output | Active-high open-drain power good output for channel 2 that is valid only when SHDN > 1.31V and VIN > 2.3V and requires a pull-up resistor; it indicates VFBX is within 4% of regulation (VFBX > 1.15V noninverting, VFBX < 65mV inverting). |+| 11 | VIN2 | power_in | Input supply pin for channel 2 that must be locally bypassed. |+| 12 | SWA2 | output | Master switch collector pin for channel 2, designed to handle a peak collector current of 1.7A (minimum), so keep the metal trace area connected to it small to reduce EMI. |+| 13 | SWB2 | output | Slave switch collector pin for channel 2, designed to handle a peak collector current of 1.3A (minimum), so keep the metal trace area connected to it small to reduce EMI. |+| 14 | CLKOUT2 | output | Clock output for channel 2 that is in phase with the internal oscillator or SYNC pin, with a duty cycle that varies with junction temperature, and is only meant to drive capacitive loads up to 120pF. |+| 15 | SHDN2 | input | Shutdown pin for channel 2 that must be driven below 0.3V to disable the channel and above 1.31V (typical) to activate it and restart soft-start, and must not be floated. |+| 16 | RT2 | passive | Timing resistor pin for channel 2 where a resistor to ground sets the fixed free-running switching frequency, and the pin must not be floated. |+| 17 | SS2 | passive | Soft-start pin for channel 2 where a soft-start capacitor is placed; at start-up it is charged by a nominal 250k resistor to about 2.1V. |+| 18 | SYNC2 | input | Synchronization input for channel 2 where the clock high level must exceed 1.3V and the low level must be below 0.4V; driving it below 0.4V reverts channel 2 to its internal free-running clock. |+| 19 | SYNC1 | input | Synchronization input for channel 1 where the clock high level must exceed 1.3V and the low level must be below 0.4V; driving it below 0.4V reverts channel 1 to its internal free-running clock. |+| 20 | SS1 | passive | Soft-start pin for channel 1 where a soft-start capacitor is placed; at start-up it is charged by a nominal 250k resistor to about 2.1V. |+| 21 | RT1 | passive | Timing resistor pin for channel 1 where a resistor to ground sets the fixed free-running switching frequency, and the pin must not be floated. |+| 22 | SHDN1 | input | Shutdown pin for channel 1 that must be driven below 0.3V to disable the channel and above 1.31V (typical) to activate it and restart soft-start, and must not be floated. |+| 23 | CLKOUT1 | output | Clock output for channel 1 that is 180° out of phase with the internal oscillator or SYNC pin with a fixed ~50% duty cycle, and is only meant to drive capacitive loads up to 120pF. |+| 24 | SWB1 | output | Slave switch collector pin for channel 1, designed to handle a peak collector current of 1.3A (minimum), so keep the metal trace area connected to it small to reduce EMI. |+| 25 | GND | power_in | Ground exposed pad that must be soldered directly to the local ground plane. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Analog Devices |+| Package | DFN-24-EP(4x7) |+| Category | Power Management ICs |+| Pins | 25 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| VIN1 Voltage | | -0.3 | | 40 | V | | 2 |+| SWA1/SWB1 Voltage | | -0.4 | | 42 | V | | 2 |+| RT1 Voltage | | -0.3 | | 5 | V | | 2 |+| SS1 Voltage | | -0.3 | | 2.5 | V | | 2 |+| FBX1 Voltage | | -0.3 | | 5 | V | | 2 |+| VC1 Voltage | | -0.3 | | 2 | V | | 2 |+| SHDN1 Voltage | | | | 40 | V | | 2 |+| SHDN1 Current | | -1 | | | mA | | 2 |+| SYNC1 Voltage | | -0.3 | | 5.5 | V | | 2 |+| GATE1 Voltage | | -0.3 | | 60 | V | | 2 |+| PG1 Voltage | | -0.3 | | 40 | V | | 2 |+| PG1 Current | | -0.5 | | 0.5 | mA | ±0.5mA as printed | 2 |+| Storage Temperature Range | | -65 | | 150 | °C | | 2 |+| Operating Junction Temperature Range | | -40 | | 125 | °C | LT8582E | 2 |+| Wide Input Range (Operating) | VIN | 2.5 | | 22 | V | Operating; 40V maximum transient (Features) | 1 |+| Maximum Junction Temperature (TJMAX) | TJMAX | | | 125 | °C | | 2 |+| Minimum Input Voltage | VIN | | 2.3 | 2.5 | V | | 3 |+| VIN Overvoltage Lockout | | 22.2 | 24.5 | 27 | V | | 3 |+| Positive Feedback Voltage | | 1.185 | 1.204 | 1.22 | V | | 3 |+| Negative Feedback Voltage | | 2 | 7 | 16 | mV | | 3 |+| Positive FBX Pin Bias Current | | 81 | 83.3 | 85 | μA | VFBX = Positive Feedback Voltage, Current into Pin | 3 |+| Negative FBX Pin Bias Current | | 81 | 83.3 | 85.5 | μA | VFBX = Negative Feedback Voltage, Current out of Pin | 3 |+| Quiescent Current | | | 2.1 | 2.5 | mA | VSHDN = 2.5V, Not Switching | 3 |+| Quiescent Current in Shutdown | | | 0 | 1 | μA | VSHDN = 0 | 3 |+| Reference Line Regulation | | | 0.01 | 0.05 | %/V | 2.5V ≤ VIN ≤ 20V | 3 |+| Switching Frequency | fOSC | 2.125 | 2.5 | 2.875 | MHz | RT = 31.6kΩ | 3 |+| Switching Frequency | fOSC | 170 | 200 | 230 | kHz | RT = 407kΩ | 3 |+| Switching Frequency Range | | 200 | | 2500 | kHz | Free-Running or Synchronizing | 3 |+| SYNC High Level for Sync | | 1.3 | | | V | | 3 |+| SYNC Low Level for Sync | | | | 0.4 | V | | 3 |+| SYNC Clock Pulse Duty Cycle | | 20 | | 80 | % | VSYNC = 0V to 2V | 3 |+| SWA Current Limit | | 1.8 | 2.4 | 3 | A | Minimum Duty Cycle | 3 |+| SWA Current Limit | | 1.3 | 1.8 | 2.5 | A | Maximum Duty Cycle | 3 |+| SWA FAULT Current Limit | | 2.2 | 2.8 | 3.5 | A | Minimum Duty Cycle | 3 |+| SWA FAULT Current Limit | | 1.6 | 2.3 | 3 | A | Maximum Duty Cycle | 3 |+| SWA + SWB Current Limit | | 3.3 | 4.3 | 5.4 | A | Minimum Duty Cycle, ISWB/ISWA = 0.79 | 3 |+| SWA + SWB Current Limit | | 2.3 | 4.1 | 4.5 | A | Maximum Duty Cycle, ISWB/ISWA = 0.79 | 3 |+| SWA + SWB FAULT Current Limit | | 4 | 5 | 6.3 | A | Minimum Duty Cycle, ISWB/ISWA = 0.79 | 3 |+| SWA + SWB FAULT Current Limit | | 2.8 | 4 | 5.4 | A | Maximum Duty Cycle, ISWB/ISWA = 0.79 | 3 |+| SS Charge Current | | 5.7 | 8.8 | 11.7 | μA | VSS = 30mV, Current Flows out of SS Pin | 3 |+| SS Discharge Current | | 5.7 | 8.8 | 11.7 | μA | Part in FAULT, VSS = 2.1V, Current Flows into SS Pin | 3 |+| SS High Detection Voltage | | 1.65 | 1.84 | 2 | V | Part in FAULT | 3 |+| SS Low Detection Voltage | | 15 | 55 | 100 | mV | Part Exiting FAULT | 3 |+| SHDN Minimum Input Voltage High | | 1.26 | 1.31 | 1.4 | V | Active Mode, SHDN Rising | 3 |+| SHDN Minimum Input Voltage High | | 1.21 | 1.27 | 1.35 | V | Active Mode, SHDN Falling | 3 |+| SHDN Input Voltage Low | | | | 0.3 | V | Shutdown Mode | 3 |+| SHDN Pin Bias Current | | 10.1 | 12.1 | 14.1 | μA | VSHDN = 3V | 4 |+| SHDN Pin Bias Current | | | 45 | 65 | μA | VSHDN = 1.3V | 4 |+| SHDN Pin Bias Current | | | 0 | 0.1 | μA | VSHDN = 0V | 4 |+| CLKOUT Output Voltage High | | 1.9 | 2.1 | 2.3 | V | 1mA out of CLKOUT Pin | 4 |+| CLKOUT Output Voltage Low | | | 30 | 200 | mV | 1mA into CLKOUT Pin | 4 |+| GATE Pull-Down Current | | 0.8 | 1 | 1.2 | mA | VGATE = 3V | 4 |+| SWA Leakage Current | | | 0.01 | 1 | μA | VSWA = 5V, VSHDN = 0 | 3 |+| SWB Leakage Current | | | 0.01 | 1 | μA | VSWB = 5V, VSHDN = 0 | 3 |+| PG Threshold for Positive Feedback Voltage | | 1.09 | 1.15 | 1.2 | V | VFBX Rising | 4 |+| PG Threshold for Negative Feedback Voltage | | 20 | 65 | 120 | mV | VFBX Falling | 4 |+| PG Output Voltage Low | | | 70 | 150 | mV | 100μA into PG Pin, VFBX = 1V | 4 |+| Thermal Resistance, Junction to Ambient | θJA | | 34 | | °C/W | | 2 |+| Thermal Resistance, Junction to Case | θJC | | 7 | | °C/W | | 2 |++## CAD (KiCad official)++- Symbol: `LT8582EDKD#PBF`+- Footprint: `Package_DFN_QFN:DFN-24-1EP_4x7mm_P0.5mm_EP2.64x6.44mm`+- 3D model: DFN-24-EP(4x7) (KiCad packages3D, STEP)+- 3D model files: `lt8582edkd-pbf-etched.step` / `lt8582edkd-pbf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lt8582edkd-pbf.step` / `lt8582edkd-pbf.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/8582f.pdf) (36 pp, sha256 `d4cd3a1bf42e8ed8`, retrieved 2026-10-28, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/lt8582edkd-pbf-datasheet.pdf)
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If not, see http://www.gnu.org/licenses/. + * + * As a special exception, if you create a design which uses this symbol, + * and embed this symbol or unaltered portions of this symbol into the design, + * this symbol does not by itself cause the resulting design to be covered by + * the GNU General Public License. + * This exception does not however invalidate any other reasons why the design + * itself might be covered by the GNU General Public License. + * If you modify this symbol, you may extend this exception to your version of the symbol, + * but you are not obligated to do so. + * If you do not wish to do so, delete this exception statement from your version + * Risk disclaimer + * *USE 3D CAD DATA AT YOUR OWN RISK* + * *DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT INDEPENDENT VERIFICATION.* + * + */ + +FILE_DESCRIPTION( +/* description */ ('model of DFN-24-1EP_4x7mm_Pitch0.5mm'), +/* implementation_level */ '2;1'); + +FILE_NAME( +/* name */ 'DFN-24-1EP_4x7mm_Pitch0.5mm.step', +/* time_stamp */ '2017-03-23T11:19:05', +/* author */ ('kicad StepUp','ksu'), +/* organization */ ('FreeCAD'), +/* preprocessor_version */ 'OCC', +/* originating_system */ 'kicad StepUp', +/* authorisation */ ''); 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package.jsonadded+337@@ -0,0 +1,337 @@+{+ "slug": "lt8582edkd-pbf",+ "version": "0.1.0",+ "type": "component",+ "description": "Analog Devices DC-DC Converters, DFN-24-EP(4x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management ics",+ "lt8582edkd#pbf",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "lt8582edkd-pbf.kicad_sym",+ "lt8582edkd-pbf.kicad_mod",+ "lt8582edkd-pbf.glb",+ "lt8582edkd-pbf.step",+ "lt8582edkd-pbf.lbr",+ "docs/hero.png",+ "docs/lt8582edkd-pbf-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "lt8582edkd-pbf-hero.glb",+ "lt8582edkd-pbf-hero.overlay.json",+ "lt8582edkd-pbf-etched.glb"+ ],+ "component": {+ "mpn": "LT8582EDKD#PBF",+ "manufacturer": "Analog Devices",+ "package": "DFN-24-EP(4x7)",+ "pin_count": 25,+ "category": "Power Management ICs",+ "subcategory": "DC-DC Converters",+ "datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/8582f.pdf",+ "parts": {+ "symbol": "lt8582edkd-pbf.kicad_sym",+ "footprint": "lt8582edkd-pbf.kicad_mod",+ "model_3d": "lt8582edkd-pbf-hero.glb",+ "model_3d_plain": "lt8582edkd-pbf-etched.glb",+ "model_3d_step": "lt8582edkd-pbf-etched.step",+ "model_3d_step_plain": "lt8582edkd-pbf.step",+ "lbr": "lt8582edkd-pbf.lbr"+ },+ "distributor_links": {+ "lcsc": "C107994",+ "digikey": "505-LT8582EDKD#PBF-ND",+ "mouser": "584-LT8582EDKD#PBF"+ },+ "distributor_check": {+ "checked_at": "2026-10-28T22:32:31Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "505-LT8582EDKD#PBF-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "584-LT8582EDKD#PBF",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "SWA1",+ "type": "output",+ "description": "Master switch collector pin for channel 1, designed to handle a peak collector current of 1.7A (minimum), so keep the metal trace area connected to it small to reduce EMI."+ },+ {+ "number": "2",+ "name": "VIN1",+ "type": "power_in",+ "description": "Input supply pin for channel 1 that must be locally bypassed."+ },+ {+ "number": "3",+ "name": "PG1",+ "type": "output",+ "description": "Active-high open-drain power good output for channel 1 that is valid only when SHDN > 1.31V and VIN > 2.3V and requires a pull-up resistor; it indicates VFBX is within 4% of regulation (VFBX > 1.15V noninverting, VFBX < 65mV inverting)."+ },+ {+ "number": "4",+ "name": "GATE1",+ "type": "output",+ "description": "PMOS gate drive pin for channel 1 that acts as a pull-down current source for output short-circuit protection or output disconnect, with a maximum pull-down current of 1mA at SS voltages above 550mV."+ },+ {+ "number": "5",+ "name": "VC1",+ "type": "passive",+ "description": "Error amplifier output for channel 1 to which the external compensation network is tied."+ },+ {+ "number": "6",+ "name": "FBX1",+ "type": "input",+ "description": "Positive and negative feedback pin for channel 1, connected to VOUT through a resistor set by the 1.204V feedback voltage and 83.3µA FBX bias current equations for noninverting or inverting converters."+ },+ {+ "number": "7",+ "name": "FBX2",+ "type": "input",+ "description": "Positive and negative feedback pin for channel 2, connected to VOUT through a resistor set by the 1.204V feedback voltage and 83.3µA FBX bias current equations for noninverting or inverting converters."+ },+ {+ "number": "8",+ "name": "VC2",+ "type": "passive",+ "description": "Error amplifier output for channel 2 to which the external compensation network is tied."+ },+ {+ "number": "9",+ "name": "GATE2",+ "type": "output",+ "description": "PMOS gate drive pin for channel 2 that acts as a pull-down current source for output short-circuit protection or output disconnect, with a maximum pull-down current of 1mA at SS voltages above 550mV."+ },+ {+ "number": "10",+ "name": "PG2",+ "type": "output",+ "description": "Active-high open-drain power good output for channel 2 that is valid only when SHDN > 1.31V and VIN > 2.3V and requires a pull-up resistor; it indicates VFBX is within 4% of regulation (VFBX > 1.15V noninverting, VFBX < 65mV inverting)."+ },+ {+ "number": "11",+ "name": "VIN2",+ "type": "power_in",+ "description": "Input supply pin for channel 2 that must be locally bypassed."+ },+ {+ "number": "12",+ "name": "SWA2",+ "type": "output",+ "description": "Master switch collector pin for channel 2, designed to handle a peak collector current of 1.7A (minimum), so keep the metal trace area connected to it small to reduce EMI."+ },+ {+ "number": "13",+ "name": "SWB2",+ "type": "output",+ "description": "Slave switch collector pin for channel 2, designed to handle a peak collector current of 1.3A (minimum), so keep the metal trace area connected to it small to reduce EMI."+ },+ {+ "number": "14",+ "name": "CLKOUT2",+ "type": "output",+ "description": "Clock output for channel 2 that is in phase with the internal oscillator or SYNC pin, with a duty cycle that varies with junction temperature, and is only meant to drive capacitive loads up to 120pF."+ },+ {+ "number": "15",+ "name": "SHDN2",+ "type": "input",+ "description": "Shutdown pin for channel 2 that must be driven below 0.3V to disable the channel and above 1.31V (typical) to activate it and restart soft-start, and must not be floated."+ },+ {+ "number": "16",+ "name": "RT2",+ "type": "passive",+ "description": "Timing resistor pin for channel 2 where a resistor to ground sets the fixed free-running switching frequency, and the pin must not be floated."+ },+ {+ "number": "17",+ "name": "SS2",+ "type": "passive",+ "description": "Soft-start pin for channel 2 where a soft-start capacitor is placed; at start-up it is charged by a nominal 250k resistor to about 2.1V."+ },+ {+ "number": "18",+ "name": "SYNC2",+ "type": "input",+ "description": "Synchronization input for channel 2 where the clock high level must exceed 1.3V and the low level must be below 0.4V; driving it below 0.4V reverts channel 2 to its internal free-running clock."+ },+ {+ "number": "19",+ "name": "SYNC1",+ "type": "input",+ "description": "Synchronization input for channel 1 where the clock high level must exceed 1.3V and the low level must be below 0.4V; driving it below 0.4V reverts channel 1 to its internal free-running clock."+ },+ {+ "number": "20",+ "name": "SS1",+ "type": "passive",+ "description": "Soft-start pin for channel 1 where a soft-start capacitor is placed; at start-up it is charged by a nominal 250k resistor to about 2.1V."+ },+ {+ "number": "21",+ "name": "RT1",+ "type": "passive",+ "description": "Timing resistor pin for channel 1 where a resistor to ground sets the fixed free-running switching frequency, and the pin must not be floated."+ },+ {+ "number": "22",+ "name": "SHDN1",+ "type": "input",+ "description": "Shutdown pin for channel 1 that must be driven below 0.3V to disable the channel and above 1.31V (typical) to activate it and restart soft-start, and must not be floated."+ },+ {+ "number": "23",+ "name": "CLKOUT1",+ "type": "output",+ "description": "Clock output for channel 1 that is 180° out of phase with the internal oscillator or SYNC pin with a fixed ~50% duty cycle, and is only meant to drive capacitive loads up to 120pF."+ },+ {+ "number": "24",+ "name": "SWB1",+ "type": "output",+ "description": "Slave switch collector pin for channel 1, designed to handle a peak collector current of 1.3A (minimum), so keep the metal trace area connected to it small to reduce EMI."+ },+ {+ "number": "25",+ "name": "GND",+ "type": "power_in",+ "description": "Ground exposed pad that must be soldered directly to the local ground plane."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The TOP VIEW pin-configuration text on page 2 is garbled in extraction, so the pin-to-name mapping w; Pin types are assigned by KiCad ERC class based on the function described in the text (for example, ; The datasheet gives the DKD package as 24-lead 7mm x 4mm plastic DFN with exposed pad pin 25, which "+ ],+ "pages_sent": 6,+ "cost_usd": 0.0617,+ "at": "2026-10-28T22:32:11"+ },+ "datasheet": {+ "url": "https://www.analog.com/media/en/technical-documentation/data-sheets/8582f.pdf",+ "pages": 36,+ "sha256": "d4cd3a1bf42e8ed8",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 25,+ "described": 25,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "lt8582edkd-pbf.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4.0,+ 6.98,+ 0.77+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "4a6878e375a298aaea2662a112301165acae02b305acab94b9c04cdc42f1b2f3",+ "checked": "2026-10-28",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "lt8582edkd-pbf-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4.0,+ 6.98,+ 0.77+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "3c79a71c6c822bb108732e6dbf8f9cae77b957aaefcbf63821483fcf529ad0ef",+ "checked": "2026-10-28",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ],+ "package_dims": {+ "package_code": "DKD24",+ "source_page": 35,+ "D": {+ "nom_mm": 7.0,+ "range_mm": [+ null,+ null+ ]+ },+ "E1": {+ "nom_mm": 4.0,+ "range_mm": [+ null,+ null+ ]+ },+ "e": {+ "nom_mm": 0.5,+ "range_mm": [+ null,+ null+ ]+ },+ "A": {+ "nom_mm": 0.75,+ "range_mm": [+ null,+ null+ ]+ },+ "source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",+ "model_check": {+ "file": "lt8582edkd-pbf.step",+ "verdict": "PASS",+ "reasons": [+ "height within the datasheet's package drawing"+ ],+ "by": "factory/package_fit.py"+ }+ }+ }+}
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management ics",+ "lt8582edkd#pbf",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "lt8582edkd-pbf.kicad_sym",+ "lt8582edkd-pbf.kicad_mod",+ "lt8582edkd-pbf.glb",+ "lt8582edkd-pbf.step",+ "lt8582edkd-pbf.lbr",+ "docs/hero.png",+ "docs/lt8582edkd-pbf-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "lt8582edkd-pbf-hero.glb",+ "lt8582edkd-pbf-hero.overlay.json",+ "lt8582edkd-pbf-etched.glb"+ ],+ "component": {+ "mpn": "LT8582EDKD#PBF",+ "manufacturer": "Analog Devices",+ "package": "DFN-24-EP(4x7)",+ "pin_count": 25,+ "category": "Power Management ICs",+ "subcategory": "DC-DC Converters",+ "datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/8582f.pdf",+ "parts": {+ "symbol": "lt8582edkd-pbf.kicad_sym",+ "footprint": "lt8582edkd-pbf.kicad_mod",+ "model_3d": "lt8582edkd-pbf-hero.glb",+ "model_3d_plain": "lt8582edkd-pbf-etched.glb",+ "model_3d_step": "lt8582edkd-pbf-etched.step",+ "model_3d_step_plain": "lt8582edkd-pbf.step",+ "lbr": "lt8582edkd-pbf.lbr"+ },+ "distributor_links": {+ "lcsc": "C107994",+ "digikey": "505-LT8582EDKD#PBF-ND",+ "mouser": "584-LT8582EDKD#PBF"+ },+ "distributor_check": {+ "checked_at": "2026-10-28T22:32:31Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "505-LT8582EDKD#PBF-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "584-LT8582EDKD#PBF",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "SWA1",+ "type": "output",+ "description": "Master switch collector pin for channel 1, designed to handle a peak collector current of 1.7A (minimum), so keep the metal trace area connected to it small to reduce EMI."+ },+ {+ "number": "2",+ "name": "VIN1",+ "type": "power_in",+ "description": "Input supply pin for channel 1 that must be locally bypassed."+ },+ {+ "number": "3",+ "name": "PG1",+ "type": "output",+ "description": "Active-high open-drain power good output for channel 1 that is valid only when SHDN > 1.31V and VIN > 2.3V and requires a pull-up resistor; it indicates VFBX is within 4% of regulation (VFBX > 1.15V noninverting, VFBX < 65mV inverting)."+ },+ {+ "number": "4",+ "name": "GATE1",+ "type": "output",+ "description": "PMOS gate drive pin for channel 1 that acts as a pull-down current source for output short-circuit protection or output disconnect, with a maximum pull-down current of 1mA at SS voltages above 550mV."+ },+ {+ "number": "5",+ "name": "VC1",+ "type": "passive",+ "description": "Error amplifier output for channel 1 to which the external compensation network is tied."+ },+ {+ "number": "6",+ "name": "FBX1",+ "type": "input",+ "description": "Positive and negative feedback pin for channel 1, connected to VOUT through a resistor set by the 1.204V feedback voltage and 83.3µA FBX bias current equations for noninverting or inverting converters."+ },+ {+ "number": "7",+ "name": "FBX2",+ "type": "input",+ "description": "Positive and negative feedback pin for channel 2, connected to VOUT through a resistor set by the 1.204V feedback voltage and 83.3µA FBX bias current equations for noninverting or inverting converters."+ },+ {+ "number": "8",+ "name": "VC2",+ "type": "passive",+ "description": "Error amplifier output for channel 2 to which the external compensation network is tied."+ },+ {+ "number": "9",+ "name": "GATE2",+ "type": "output",+ "description": "PMOS gate drive pin for channel 2 that acts as a pull-down current source for output short-circuit protection or output disconnect, with a maximum pull-down current of 1mA at SS voltages above 550mV."+ },+ {+ "number": "10",+ "name": "PG2",+ "type": "output",+ "description": "Active-high open-drain power good output for channel 2 that is valid only when SHDN > 1.31V and VIN > 2.3V and requires a pull-up resistor; it indicates VFBX is within 4% of regulation (VFBX > 1.15V noninverting, VFBX < 65mV inverting)."+ },+ {+ "number": "11",+ "name": "VIN2",+ "type": "power_in",+ "description": "Input supply pin for channel 2 that must be locally bypassed."+ },+ {+ "number": "12",+ "name": "SWA2",+ "type": "output",+ "description": "Master switch collector pin for channel 2, designed to handle a peak collector current of 1.7A (minimum), so keep the metal trace area connected to it small to reduce EMI."+ },+ {+ "number": "13",+ "name": "SWB2",+ "type": "output",+ "description": "Slave switch collector pin for channel 2, designed to handle a peak collector current of 1.3A (minimum), so keep the metal trace area connected to it small to reduce EMI."+ },+ {+ "number": "14",+ "name": "CLKOUT2",+ "type": "output",+ "description": "Clock output for channel 2 that is in phase with the internal oscillator or SYNC pin, with a duty cycle that varies with junction temperature, and is only meant to drive capacitive loads up to 120pF."+ },+ {+ "number": "15",+ "name": "SHDN2",+ "type": "input",+ "description": "Shutdown pin for channel 2 that must be driven below 0.3V to disable the channel and above 1.31V (typical) to activate it and restart soft-start, and must not be floated."+ },+ {+ "number": "16",+ "name": "RT2",+ "type": "passive",+ "description": "Timing resistor pin for channel 2 where a resistor to ground sets the fixed free-running switching frequency, and the pin must not be floated."+ },+ {+ "number": "17",+ "name": "SS2",+ "type": "passive",+ "description": "Soft-start pin for channel 2 where a soft-start capacitor is placed; at start-up it is charged by a nominal 250k resistor to about 2.1V."+ },+ {+ "number": "18",+ "name": "SYNC2",+ "type": "input",+ "description": "Synchronization input for channel 2 where the clock high level must exceed 1.3V and the low level must be below 0.4V; driving it below 0.4V reverts channel 2 to its internal free-running clock."+ },+ {+ "number": "19",+ "name": "SYNC1",+ "type": "input",+ "description": "Synchronization input for channel 1 where the clock high level must exceed 1.3V and the low level must be below 0.4V; driving it below 0.4V reverts channel 1 to its internal free-running clock."+ },+ {+ "number": "20",+ "name": "SS1",+ "type": "passive",+ "description": "Soft-start pin for channel 1 where a soft-start capacitor is placed; at start-up it is charged by a nominal 250k resistor to about 2.1V."+ },+ {+ "number": "21",+ "name": "RT1",+ "type": "passive",+ "description": "Timing resistor pin for channel 1 where a resistor to ground sets the fixed free-running switching frequency, and the pin must not be floated."+ },+ {+ "number": "22",+ "name": "SHDN1",+ "type": "input",+ "description": "Shutdown pin for channel 1 that must be driven below 0.3V to disable the channel and above 1.31V (typical) to activate it and restart soft-start, and must not be floated."+ },+ {+ "number": "23",+ "name": "CLKOUT1",+ "type": "output",+ "description": "Clock output for channel 1 that is 180° out of phase with the internal oscillator or SYNC pin with a fixed ~50% duty cycle, and is only meant to drive capacitive loads up to 120pF."+ },+ {+ "number": "24",+ "name": "SWB1",+ "type": "output",+ "description": "Slave switch collector pin for channel 1, designed to handle a peak collector current of 1.3A (minimum), so keep the metal trace area connected to it small to reduce EMI."+ },+ {+ "number": "25",+ "name": "GND",+ "type": "power_in",+ "description": "Ground exposed pad that must be soldered directly to the local ground plane."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The TOP VIEW pin-configuration text on page 2 is garbled in extraction, so the pin-to-name mapping w; Pin types are assigned by KiCad ERC class based on the function described in the text (for example, ; The datasheet gives the DKD package as 24-lead 7mm x 4mm plastic DFN with exposed pad pin 25, which "+ ],+ "pages_sent": 6,+ "cost_usd": 0.0617,+ "at": "2026-10-28T22:32:11"+ },+ "datasheet": {+ "url": "https://www.analog.com/media/en/technical-documentation/data-sheets/8582f.pdf",+ "pages": 36,+ "sha256": "d4cd3a1bf42e8ed8",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 25,+ "described": 25,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "lt8582edkd-pbf.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4,+ 6.98,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "4a6878e375a298aaea2662a112301165acae02b305acab94b9c04cdc42f1b2f3",+ "checked": "2026-10-28",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "lt8582edkd-pbf-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4,+ 6.98,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3c79a71c6c822bb108732e6dbf8f9cae77b957aaefcbf63821483fcf529ad0ef",+ "checked": "2026-10-28",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ],+ "package_dims": {+ "package_code": "DKD24",+ "source_page": 35,+ "D": {+ "nom_mm": 7,+ "range_mm": [+ null,+ null+ ]+ },+ "E1": {+ "nom_mm": 4,+ "range_mm": [+ null,+ null+ ]+ },+ "e": {+ "nom_mm": 0.5,+ "range_mm": [+ null,+ null+ ]+ },+ "A": {+ "nom_mm": 0.75,+ "range_mm": [+ null,+ null+ ]+ },+ "source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",+ "model_check": {+ "file": "lt8582edkd-pbf.step",+ "verdict": "PASS",+ "reasons": [+ "height within the datasheet's package drawing"+ ],+ "by": "factory/package_fit.py"+ }+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}
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