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LT6600CS8-10#PBF

Analog Devices · Pre-ordered Chips · SO-8

LT6600CS8-10#PBF from Analog Devices, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IN-	input	Inverting filter input, driven through an external resistor RIN, with DC differential gain of 402Ω/RIN (page 8) and input current limited to under 10mA if the differential input exceeds 1.4V.
2	VOCM	input	High-impedance DC common-mode reference for the 2nd filter stage that sets the output common-mode voltage; it can be tied to VMID or an external reference and should be bypassed with 0.01µF unless connected to a ground plane.
3	V+	power_in	Positive supply pin, needing a quality 0.1µF ceramic bypass capacitor to V- placed as close to the IC as possible, with a total supply voltage of at most 11V.
4	OUT+	output	Non-inverting differential filter output that can drive a 100Ω and/or 50pF load to AC ground.
5	OUT-	output	Inverting differential filter output that can drive a 100Ω and/or 50pF load to AC ground.
6	V-	power_in	Negative supply pin (ground for single-supply operation) that is fused to the lead frame for thermal conduction, with a 0.1µF ceramic bypass to V+ (or to ground in dual-supply use).
7	VMID	bidirectional	Internally mid-supply-biased pin with about 5.5kΩ impedance that sets the output common mode of the 1st filter stage; bypass it with 0.01µF to V- and, if overridden, keep it at least 1.5V from either supply rail.
8	IN+	input	Non-inverting filter input, driven through an external resistor RIN, with DC differential gain of 402Ω/RIN (page 8) and input current limited to under 10mA if the differential input exceeds 1.4V.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	SO-8
Category	Interface ICs
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Filter Gain, VS = 3V		-0.4	0	0.5	dB	VS = 3V, VIN = 2VP-P, fIN = DC to 260kHz	3
Filter Gain 1MHz rel 260kHz, VS = 3V		-0.1	0	0.1	dB	VS = 3V, VIN = 2VP-P, fIN = 1MHz (gain relative to 260kHz)	3
Filter Gain 5MHz rel 260kHz, VS = 3V		-0.4	-0.1	0.3	dB	VS = 3V, VIN = 2VP-P, fIN = 5MHz (gain relative to 260kHz)	3
Filter Gain 8MHz rel 260kHz, VS = 3V		-0.3	0.1	1	dB	VS = 3V, VIN = 2VP-P, fIN = 8MHz (gain relative to 260kHz)	3
Filter Gain 10MHz rel 260kHz, VS = 3V		-0.2	0.3	1.7	dB	VS = 3V, VIN = 2VP-P, fIN = 10MHz (gain relative to 260kHz)	3
Filter Gain 30MHz rel 260kHz, VS = 3V		-28		-25	dB	VS = 3V, VIN = 2VP-P, fIN = 30MHz (gain relative to 260kHz)	3
Filter Gain 50MHz rel 260kHz, VS = 3V				-44	dB	VS = 3V, VIN = 2VP-P, fIN = 50MHz (gain relative to 260kHz)	3
Filter Gain, VS = 5V		-0.5	0	0.5	dB	VS = 5V, VIN = 2VP-P, fIN = DC to 260kHz	3
Filter Gain 1MHz rel 260kHz, VS = 5V		-0.1	0	0.1	dB	VS = 5V, VIN = 2VP-P, fIN = 1MHz (gain relative to 260kHz)	4
Filter Gain 5MHz rel 260kHz, VS = 5V		-0.4	-0.1	0.3	dB	VS = 5V, VIN = 2VP-P, fIN = 5MHz (gain relative to 260kHz)	3
Filter Gain 8MHz rel 260kHz, VS = 5V		-0.4	0.1	0.9	dB	VS = 5V, VIN = 2VP-P, fIN = 8MHz (gain relative to 260kHz)	3
Filter Gain 10MHz rel 260kHz, VS = 5V		-0.3	0.2	1.4	dB	VS = 5V, VIN = 2VP-P, fIN = 10MHz (gain relative to 260kHz)	3
Filter Gain, VS = ±5V		-0.6	-0.1	0.4	dB	VS = ±5V, VIN = 2VP-P, fIN = DC to 260kHz	3
Filter Gain, RIN = 100Ω		11.4	12	12.6	dB	RIN = 100Ω, VS = 3V, 5V, ±5V, VIN = 0.5VP-P, fIN = DC to 260kHz	3
Differential Output Swing VS = 5V		3.85		5	VP-P DIFF	Measured between pins 4 and 5, VS = 5V	3
Differential Output Swing, pin 7 shorted to pin 2, VS = 3V		3.85		4.9	VP-P DIFF	Measured between pins 4 and 5, pin 7 shorted to pin 2, VS = 3V	3
Input Bias Current		-85		-40	μA	Average of pin 1 and pin 8	3
Input Referred Differential Offset, RIN = 402Ω, VS = 3V		5		10	mV	RIN = 402Ω, VS = 3V	3
Input Referred Differential Offset, RIN = 402Ω, VS = 5V		8		20	mV	RIN = 402Ω, VS = 5V	3
Input Referred Differential Offset, RIN = 402Ω, VS = ±5V		30		35	mV	RIN = 402Ω, VS = ±5V	3
Input Referred Differential Offset, RIN = 100Ω, VS = 3V		5		13	mV	RIN = 100Ω, VS = 3V	3
Input Referred Differential Offset, RIN = 100Ω, VS = 5V		5		22	mV	RIN = 100Ω, VS = 5V	3
Input Referred Differential Offset, RIN = 100Ω, VS = ±5V		5		30	mV	RIN = 100Ω, VS = ±5V	3
Input Common Mode Voltage, RIN = 100Ω, VS = 3V		0		1.5	V	Differential input = 500mVP-P, VS = 3V	4
Input Common Mode Voltage, RIN = 100Ω, VS = 5V		0		3	V	RIN = 100Ω, VS = 5V	4
Input Common Mode Voltage, RIN = 100Ω, VS = ±5V		-2.5		1	V	RIN = 100Ω, VS = ±5V	4
Output Common Mode Offset (with respect to pin 2), VS = 3V		-35	5	40	mV	VS = 3V	4
Output Common Mode Offset (with respect to pin 2), VS = 5V		-40	0	40	mV	VS = 5V	4
Output Common Mode Offset (with respect to pin 2), VS = ±5V		-55	-5	35	mV	VS = ±5V	4
Voltage at VMID (Pin 7), VS = 5V (S8)		2.46		2.51	V	VS = 5V (S8)	4
VMID Input Resistance		4.3	5.5	7.7	kΩ		4
VOCM Bias Current, VS = 5V		-15		-3	μA	VOCM = VMID = VS/2, VS = 5V	4
VOCM Bias Current, VS = 3V		-10		-3	μA	VOCM = VMID = VS/2, VS = 3V	4
Differential Offset Drift			10		μV/°C		3
Filter Gain Temperature Coefficient			780		ppm/C	fIN = 260kHz, VIN = 2VP-P	3
Total Supply Voltage				11	V		2
Input Current		-10		10	mA	Note 8	2
Operating Temperature Range		-40		85	°C	Note 6	2
Specified Temperature Range		-40		85	°C	Note 7	2
Junction Temperature	TJMAX			150	°C		2
Storage Temperature Range		-65		150	°C		2
Lead Temperature				300	°C	Soldering, 10 sec	2
Thermal Resistance, junction-to-ambient (S8)	θJA		100		°C/W	S8 package	2
Thermal Resistance, junction-to-ambient, 1100/1100 mm2 copper	θJA		65		°C/W	Topside 1100 mm2, backside 1100 mm2, board area 2500 mm2	12
Thermal Resistance, junction-to-ambient, 330/330 mm2 copper	θJA		85		°C/W	Topside 330 mm2, backside 330 mm2, board area 2500 mm2	12
Thermal Resistance, junction-to-ambient, 35/35 mm2 copper	θJA		95		°C/W	Topside 35 mm2, backside 35 mm2, board area 2500 mm2	12
Thermal Resistance, junction-to-ambient, 35/0 mm2 copper	θJA		100		°C/W	Topside 35 mm2, backside 0 mm2, board area 2500 mm2	12
Thermal Resistance, junction-to-ambient, 0/0 mm2 copper	θJA		105		°C/W	Topside 0 mm2, backside 0 mm2, board area 2500 mm2	12

CAD (KiCad official)

Symbol: LT6600CS8-10#PBF
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SO-8 (KiCad packages3D, STEP)
3D model files: lt6600cs8-10-pbf-etched.step / lt6600cs8-10-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt6600cs8-10-pbf.step / lt6600cs8-10-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (16 pp, sha256 851e4743956f67b6, retrieved 2026-10-28, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF