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LT3845EFE#TRPBF
Public Made by Adomby adom
Analog Devices DC-DC Converters, TSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
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LT3845EFE#TRPBF
Analog Devices · DC-DC Converters · TSSOP-16-EP
LT3845EFE#TRPBF from Analog Devices, in a TSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Main supply pin, to be decoupled to SGND with a low ESR capacitor of at least 0.1μF located close to the pin; the part operates from a 4V to 60V input range. |
| 2 | SHDN | input | Enable pin with a precision 1.35V rising threshold and 120mV hysteresis; pulling it below about 0.7V enters low-current shutdown, and the pin is internally clamped to 6V with an absolute maximum of 5V. |
| 3 | CSS | passive | Soft-start capacitor pin, where CSS = 2μA(tSS/1.231V) sets the output voltage slew rate, and it should be left unconnected when soft-start is not used. |
| 4 | BURST_EN | input | Below 0.5V enables Burst Mode operation and reverse-current inhibit, above 0.5V disables Burst Mode while keeping reverse-current inhibit, and connecting it to VCC disables both; absolute maximum is 24V. |
| 5 | VFB | input | Output voltage feedback input to the inverting input of the error amplifier, which regulates VFB at 1.231V through an external resistive divider; absolute maximum is 5V. |
| 6 | VC | passive | Error amplifier output that sets the peak switch current per cycle and is typically compensated with an RC network to SGND; it must not be pulled low by a low impedance source and should be driven through a 1kΩ series resistance if externally manipulated. |
| 7 | SYNC | input | External clock input for synchronizing the oscillator, with RSET set so the internal oscillator runs 10% to 25% below the external clock within a 100kHz to 600kHz sync range; connect to SGND if unused, and the absolute maximum is 5V. |
| 8 | fSET | passive | Programs the oscillator frequency with an external resistor RSET, which is required even when an external sync clock is applied. |
| 9 | SENSE- | input | Negative input of the current sense amplifier, connected to the VOUT side of the sense resistor in step-down applications; the sensed inductor current limit is ±100mV across the SENSE inputs and the absolute maximum voltage is 40V. |
| 10 | SENSE+ | input | Positive input of the current sense amplifier, connected to the inductor side of the sense resistor in step-down applications; the sensed inductor current limit is ±100mV across the SENSE inputs and the absolute maximum voltage is 40V. |
| 11 | PGND | power_in | High-current ground reference for the internal low-side switch driver and the VCC regulator, to be connected directly to the negative terminal of the VCC decoupling capacitor. |
| 12 | BG | output | Gate drive for the bottom N-channel MOSFET, to be connected with a short, wide (about 0.02 in) PCB trace to minimize inductance. |
| 13 | VCC | power_out | Internal bias supply decoupling node that requires a low ESR ceramic capacitor of 1μF or greater to PGND; the absolute maximum rating is 24V. |
| 14 | SW | passive | Reference for the VBOOST supply and the high current return for the bootstrapped switch; the absolute maximum switch voltage is 65V to -2V. |
| 15 | TG | output | Bootstrapped gate drive for the top N-channel MOSFET, to be connected with a short, wide (about 0.02 in) PCB trace to minimize inductance. |
| 16 | BOOST | power_in | Supply for the bootstrapped gate drive, connected to a low ESR ceramic boost capacitor referenced to SW (0.1μF is typical, at least 50 times the top MOSFET gate capacitance); the maximum voltage on this pin is VIN + VCC, ground referred. |
| 17 | SGND | power_in | Exposed pad and low-noise ground reference, internally connected to the SGND pin, which must be soldered to the PCB ground for electrical and thermal performance and connected to the -VOUT side of the output capacitors. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-16-EP |
| Category | Power Management ICs |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Supply Voltage (VIN) absolute maximum | VIN | 65 | V | 2 | |||
| Switch Voltage (SW) | SW | -2 | 65 | V | -2V is a transient (Note 8) | 2 | |
| SENSE+ and SENSE- Voltages | VSENSE+, VSENSE- | 40 | V | 2 | |||
| Differential Sense Voltage (SENSE+ to SENSE-) | VSENSE+ - VSENSE- | -1 | 1 | V | 2 | ||
| SYNC, VC, VFB, CSS, and SHDN Voltages | 5 | V | 2 | ||||
| SHDN Pin Current | ISHDN | 1 | mA | 2 | |||
| Storage Temperature | TSTG | -65 | 150 | °C | 2 | ||
| Lead Temperature (Soldering) | 300 | °C | Soldering, 10 sec | 2 | |||
| Operating Junction Temperature Range (LT3845E) | TJ | -40 | 125 | °C | LT3845E (Note 3) | 2 | |
| Thermal resistance, junction to ambient (FE TSSOP) | θJA | 40 | °C/W | FE package | 2 | ||
| Thermal resistance, junction to case (FE TSSOP) | θJC | 10 | °C/W | FE package | 2 | ||
| VIN Operating Voltage Range | VIN | 4 | 60 | V | 3 | ||
| VIN Minimum Start Voltage | VIN | 7.5 | V | 3 | |||
| VIN UVLO Threshold (Falling) | VIN UVLO | 3.6 | 3.8 | 4 | V | 3 | |
| VIN Shutdown Current | IVIN(SHDN) | 9 | 15 | μA | VSHDN = 0V | 3 | |
| Error Amp Reference Voltage (measured at VFB pin) | VFB | 1.224 | 1.231 | 1.238 | V | Over full operating temperature range | 3 |
| SHDN Enable Threshold (Rising) | VSHDN | 1.3 | 1.35 | 1.4 | V | Over full operating temperature range | 3 |
| Sense Pins Common Mode Range | VSENSE(CM) | 0 | 36 | V | 3 | ||
| Current Limit Sense Voltage | VSENSE+ - VSENSE- | 90 | 100 | 115 | mV | VSENSE+ - VSENSE- | 3 |
| Operating Frequency | fSW | 270 | 300 | 330 | kHz | Over full operating temperature range | 3 |
| Minimum Programmable Frequency | fSW(MIN) | 100 | kHz | Over full operating temperature range | 3 | ||
| Maximum Programmable Frequency | fSW(MAX) | 500 | kHz | Over full operating temperature range | 3 | ||
| External Sync Frequency Range | fSYNC | 100 | 600 | kHz | Over full operating temperature range | 3 | |
| SYNC Voltage Threshold | VSYNC | 1.4 | 2 | V | Over full operating temperature range | 3 | |
| Error Amp Transconductance | gm | 270 | 340 | 410 | μS | Over full operating temperature range | 3 |
| Error Amp Sink/Source Current | IEA | -30 | 30 | μA | 3 | ||
| Minimum TG Off Time | tOFF(MIN) | 350 | 650 | ns | Over full operating temperature range | 4 | |
| Minimum TG On Time | tON(MIN) | 250 | 400 | ns | Over full operating temperature range | 4 | |
| VCC Output Voltage | VCC | 8 | 8.3 | V | Over full line and load range | 3 |
CAD (KiCad official)
- Symbol:
LT3845EFE#TRPBF - Footprint:
Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm - 3D model: TSSOP-16-EP (KiCad packages3D, STEP)
- 3D model files:
lt3845efe-trpbf-etched.step/lt3845efe-trpbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lt3845efe-trpbf.step/lt3845efe-trpbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (26 pp, sha256
1d802d74ecb7d372, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).