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LT3042EDD#PBF

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Analog Devices Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, DFN-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LT3042EDD#PBF

Analog Devices · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DFN-10-EP(3x3)

LT3042EDD#PBF from Analog Devices, in a DFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input supply pin; a 4.7µF bypass capacitor is the minimum, and the pin withstands reverse voltage with respect to GND, OUTS and OUT (±22V absolute maximum on IN).
2 IN power_in Second input supply pin, internally common with pin 1; a 4.7µF bypass capacitor is the minimum and reverse-voltage withstand applies as for pin 1.
3 EN/UV input Enable/UVLO pin; pulling it low shuts the part down with quiescent current below 1µA, it turns on above a 1.24V rising threshold with 170mV hysteresis, and it must not be left floating (tie to IN if unused).
4 PG output Open-collector power good flag that pulls low when PGFB is below 300mV, must not be driven more than 0.3V below GND, and may be left floating if unused.
5 ILIM passive Current limit programming pin; a resistor to GND sets the limit with a nominal 125mA•kΩ scale factor (Kelvin connected to GND), it sources current 1:400 of the output current for monitoring over a 0V to 300mV range, and it should be tied to GND if unused.
6 PGFB input Power good feedback pin; PG releases when PGFB rises above 300mV with 7mV falling hysteresis, it sets the programmable threshold via an external divider from OUT, it activates fast start-up below 300mV, and it should be tied to IN if power good and fast start-up are not used.
7 SET passive Error amplifier inverting input and regulation set-point; it sources a precision 100µA through the external resistor to GND so that VOUT = ISET • RSET over a 0V to 15V output range, and must not be driven more than 0.3V below GND.
8 GND power_in Ground pin, which must be tied directly to the exposed backside pad and the PCB ground for proper electrical and thermal performance.
9 OUTS input Output sense pin, the noninverting input of the error amplifier, which should be Kelvin connected directly to the output capacitor and load and must not be driven more than 0.3V below GND.
10 OUT power_out Output pin that supplies the load and requires a minimum 4.7µF ceramic output capacitor with ESR below 50mΩ and ESL below 2nH for stability.
11 GND power_in Exposed pad, electrically GND, which must be soldered to the PCB ground for electrical and thermal performance.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package DFN-10-EP(3x3)
Category Power Management (PMIC)
Pins 11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
IN Pin Voltage -22 22 V 2
EN/UV Pin Voltage -22 22 V 2
IN-to-EN/UV Differential -22 22 V 2
PG Pin Voltage -0.3 22 V Note 10 2
ILIM Pin Voltage -0.3 1 V Note 10 2
PGFB Pin Voltage -0.3 22 V Note 10 2
SET Pin Voltage -0.3 16 V Note 10 2
SET Pin Current -20 20 mA Note 7 2
OUTS Pin Voltage -0.3 16 V Note 10 2
OUTS Pin Current -20 20 mA Note 7 2
OUT Pin Voltage -0.3 16 V Note 10 2
OUT-to-OUTS Differential -1.2 1.2 V Note 14 2
IN-to-OUT Differential -22 22 V 2
IN-to-OUTS Differential -22 22 V 2
Storage Temperature Range -65 150 °C 2
Input Voltage Range 1.8 20 V Wide Input Voltage Range (Features) 1
Output Voltage Range 0 15 V Output Voltage Range (Features) 1
Minimum Output Capacitor COUT 4.7 µF Ceramic; ESR below 50mΩ and ESL below 2nH 15
Operating Junction Temperature Range (E-grade) TJ -40 125 °C E-, I-Grade 2
Minimum IN Pin Voltage 1.78 2 V ILOAD = 200mA, VIN UVLO Rising 3
SET Pin Current (ISET) ISET 99 100 101 µA VIN = 2V, ILOAD = 1mA, VOUT = 1.3V 3
SET Pin Current (ISET) ISET 98 100 102 µA 2V < VIN < 20V, 0V < VOUT < 15V, 1mA < ILOAD < 200mA (Note 3) 3
Output Offset Voltage VOS (VOUT, VSET) VOS -1 1 mV VIN = 2V, ILOAD = 1mA, VOUT = 1.3V 3
Output Offset Voltage VOS (VOUT, VSET) VOS -2 2 mV 2V < VIN < 20V, 0V < VOUT < 15V, 1mA < ILOAD < 200mA (Note 3) 3
Line Regulation ΔISET ΔISET -2 0.5 2 nA/V VIN = 2V to 20V, ILOAD = 1mA, VOUT = 1.3V 3
Line Regulation ΔVOS ΔVOS -3 0.5 3 µV/V VIN = 2V to 20V, ILOAD = 1mA, VOUT = 1.3V (Note 4) 3
Load Regulation ΔVOS ΔVOS 0.1 0.5 mV ILOAD = 1mA to 200mA, VIN = 2V, VOUT = 1.3V (Note 4) 3
Change in ISET with VSET ISET 30 150 nA VSET = 1.3V to 15V, VIN = 20V, ILOAD = 1mA 3
Change in VOS with VSET VOS 0.03 0.3 mV VSET = 1.3V to 15V, VIN = 20V, ILOAD = 1mA (Note 4) 3
Change in ISET with VSET ISET 400 600 nA VSET = 0V to 1.3V, VIN = 20V, ILOAD = 1mA 3
Change in VOS with VSET VOS 0.6 2 mV VSET = 0V to 1.3V, VIN = 20V, ILOAD = 1mA (Note 4) 3
EN/UV Pin Threshold (Trip Point Rising, Turn-On) 1.18 1.24 1.32 V VIN = 2V 3
Programmable Current Limit 180 200 220 mA VIN = 2V, VOUT = 0V, RILIM = 625Ω 4
Programmable Current Limit 45 50 55 mA VIN = 2V, VOUT = 0V, RILIM = 2.5kΩ 4
PGFB Trip Point Rising 291 300 309 mV 4
PG Output Low Voltage 30 100 mV IPG = 100µA 4
PG Leakage Current 1 µA VPG = 20V 4
Reverse Input Current 50 µA VIN = -20V, VEN/UV = 0V, VOUT = 0V, VSET = 0V 4
Reverse Output Current 2 5 µA VIN = 0, VOUT = 5V, SET = Open 4
Minimum Load Required 10 µA VOUT < 1V 4
Quiescent Current in Shutdown 0.3 1 µA VEN/UV = 0V, VIN = 6V 4
Quiescent Current in Shutdown 10 µA VEN/UV = 0V, VIN = 6V (l, full operating temperature range) 4
Maximum Junction Temperature TJMAX 150 °C Pin configuration, DD package 2
Thermal Resistance, Junction-to-Ambient θJA 34 °C/W DD package (10-lead 3mm × 3mm DFN) 2
Thermal Resistance, Junction-to-Case θJC 5.5 °C/W DD package (10-lead 3mm × 3mm DFN) 2

CAD (KiCad official)

  • Symbol: LT3042EDD#PBF
  • Footprint: Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm
  • 3D model: DFN-10-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: lt3042edd-pbf-etched.step / lt3042edd-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt3042edd-pbf.step / lt3042edd-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (32 pp, sha256 c65c2b7406029d9b, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF