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LP873344RHDRQ1

Public Made by Adom

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Texas Instruments DC-DC Converters, VQFN-28(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)lp873344rhdrq1factory-2.0.0extractor-text
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LP873344RHDRQ1

Texas Instruments · DC-DC Converters · VQFN-28(5x5)

LP873344RHDRQ1 from Texas Instruments, in a VQFN-28(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUT_LDO0 power_out LDO0 regulated output; leave the pin floating if LDO0 is not used.
2 FB_B0 input Positive output voltage feedback input for Buck 0.
3 FB_B1 input Positive output voltage feedback input for Buck 1 in two single-phase configuration, and negative output ground feedback for Buck 0 in dual-phase configuration.
4 AGND power_in Ground pin.
5 VANA power_in Supply voltage for analog and digital blocks; must be connected to the same node as VIN_Bx (2.8 V to 5.5 V recommended operating range).
6 EN input Programmable enable signal for regulators and GPOs; leave floating if the pin is not used.
7 VOUT_LDO1 power_out LDO1 regulated output; leave the pin floating if LDO1 is not used.
8 VIN_LDO1 power_in Power input for LDO1 (2.5 V to 5.5 V recommended); connect to VANA if LDO1 is not used.
9 nINT output Open-drain interrupt output, active LOW; connect to ground if the pin is not used.
10 CLKIN bidirectional External clock input with alternative function general-purpose digital output GPO2; leave floating if not used.
11 VIN_B1 power_in Input for Buck 1; VIN_Bx pins are not connected together internally and must be connected together in the application and locally bypassed.
12 VIN_B1 power_in Input for Buck 1; VIN_Bx pins are not connected together internally and must be connected together in the application and locally bypassed.
13 SW_B1 power_out Buck 1 switch node; leave the pin floating if Buck 1 is not used.
14 SW_B1 power_out Buck 1 switch node; leave the pin floating if Buck 1 is not used.
15 PGND_B1 power_in Power ground for Buck 1.
16 PGND_B1 power_in Power ground for Buck 1.
17 SCL input Serial interface clock input for I2C access; connect a pullup resistor, or connect to ground if the I2C interface is not used.
18 SDA bidirectional Serial interface data input and output for I2C access; connect a pullup resistor, or connect to ground if the I2C interface is not used.
19 SGND power_in Ground pin.
20 PGND_B0 power_in Power ground for Buck 0.
21 PGND_B0 power_in Power ground for Buck 0.
22 SW_B0 power_out Buck 0 switch node; leave the pin floating if Buck 0 is not used.
23 SW_B0 power_out Buck 0 switch node; leave the pin floating if Buck 0 is not used.
24 VIN_B0 power_in Input for Buck 0; VIN_Bx pins are not connected together internally and must be connected together in the application and locally bypassed.
25 VIN_B0 power_in Input for Buck 0; VIN_Bx pins are not connected together internally and must be connected together in the application and locally bypassed.
26 GPO output General-purpose digital output; leave the pin floating if not used.
27 PGOOD output Power-good indication signal; leave the pin floating if not used.
28 VIN_LDO0 power_in Power input for LDO0 (2.5 V to 5.5 V recommended); connect to VANA if LDO0 is not used.
29 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-28(5x5)
Category Power Management (PMIC)
Pins 29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Voltage on power connections VIN_Bx, VANA (must use same input supply) -0.3 6 V Over operating free-air temperature range 5
Voltage on power connections VIN_LDOx -0.3 6 V Over operating free-air temperature range 5
Voltage on buck switch nodes SW_Bx -0.3 V 5
Voltage on buck voltage sense nodes FB_Bx -0.3 V 5
Voltage on LDO output VOUT_LDOx -0.3 V 5
Voltage on logic pins SDA, SCL, nINT, EN -0.3 6 V Input or output pins 5
Voltage on logic pins PGOOD, GPO, CLKIN (GPO2) -0.3 V Input or output pins 5
Junction temperature TJ-MAX -40 150 °C Over operating free-air temperature range 5
Storage temperature Tstg -65 150 °C 5
Maximum lead temperature 260 Soldering, 10 seconds 5
Input voltage range VIN_Bx, VANA 2.8 5.5 V VIN_Bx and VANA must be connected to the same input supply 5
Voltage on LDO inputs VIN_LDOx 2.5 5.5 V 5
Voltage on logic pins EN, nINT 0 5.5 V Input or output pins 5
Voltage on logic input pin CLKIN 0 V Input pin 5
Voltage on logic output pins PGOOD, GPO, GPO2 0 V Output pins 5
Voltage on I2C interface SCL, SDA 0 1.95 V Standard (100 kHz), Fast (400 kHz), Fast+ (1 MHz), High-Speed (3.4 MHz) modes 5
Voltage on I2C interface SCL, SDA 0 V Standard (100 kHz), Fast (400 kHz), Fast+ (1 MHz) modes 5
Junction temperature TJ -40 140 °C 5
Ambient temperature TA -40 125 °C 5
Effective output filtering capacitance per phase COUT_BUCK COUT_BUCK 10 22 500 µF Effective capacitance per phase 6
Output filtering capacitance for LDO regulators COUT_LDO 0.4 1 2.7 µF Effective capacitance 6
Inductance of the inductor (tolerance) L -30 30 % Printed tolerance –30% / 30% of 0.47 µH 6
Input voltage range V(VIN_Bx), V(VANA) V(VIN_Bx), V(VANA) 2.8 3.7 5.5 V VIN_Bx and VANA pins must be connected to the same supply line 6
Buck output voltage programmable range VOUT_Bx 0.7 1 3.36 V Programmable voltage range 6
DC output voltage accuracy VOUT_Bx_DC -20 20 mV Force PWM mode, VOUT < 1 V 7
DC output voltage accuracy VOUT_Bx_DC -2 2 % Force PWM mode, VOUT ≥ 1 V 7
DC output voltage accuracy VOUT_Bx_DC -20 40 mV PFM mode, VOUT < 1 V, the average output voltage level is increased by max. 20 mV 7
Transient load step response, single-phase output TLDSR -55 55 mV IOUT = 0.1 A to 2 A, TR = TF = 400 ns, PWM mode 7
Transient load step response, dual-phase output TLDSR -50 50 mV IOUT = 0.1 A to 4 A, TR = TF = 400 ns, PWM mode 7
Forward current limit per phase programmable range ILIM FWD 1.5 4 A Programmable range 7
Forward current limit accuracy ILIM FWD -5 7.5 20 % V(VIN_Bx) ≥ 3 V, ILIM = 4 A 7
Negative current limit per phase ILIM NEG 1.6 2 3 A 7
Switching frequency ƒSW 1.8 2 2.2 MHz PWM mode 7
Overvoltage threshold for PGOOD and power-good interrupt (buck) 39 50 64 mV V(VIN_Bx), V(VANA) fixed 3.7 V; compared to DC output voltage level VOUT_Bx_DC 8
Undervoltage threshold for PGOOD and power-good interrupt (buck) -53 -40 -29 mV V(VIN_Bx), V(VANA) fixed 3.7 V; compared to DC output voltage level VOUT_Bx_DC 8
Output pulldown resistance (buck) RDIS_Bx 150 250 350 Ω Regulator disabled 8
Buck short-circuit detection threshold 280 360 440 mV 9
Input voltage range for LDO power inputs VIN_LDOx VIN_LDOx 2.5 3.7 5.5 V VIN_LDOx can be higher or lower than V(VANA) 8
LDO output voltage programmable range VOUT_LDOx 0.8 3.3 V Programmable voltage range 8
DC output voltage accuracy (LDO) VOUT_LDO_DC -20 20 mV VOUT < 1 V 8
DC output voltage accuracy (LDO) VOUT_LDO_DC -2 2 % VOUT ≥ 1 V 8
Transient load step response (LDO) TLDSR -50 40 mV IOUT = 1 mA to 300 mA, TR = TF = 1 µs 8
LDO current limit ISHORT(LDOx) 400 500 600 mA VOUT = 0 V 8
Output pulldown resistance (LDO) RDIS_LDOx 150 250 350 Ω Regulator disabled 8
LDO short-circuit detection threshold 190 300 450 mV 9
External input clock nominal frequency fEXT_CLK 1 24 MHz Nominal frequency 9
Required accuracy from nominal frequency (external clock) fEXT_CLK -30 10 % 9
Thermal warning threshold (TDIE_WARN_LEVEL = 0) 115 125 135 °C Temperature rising, TDIE_WARN_LEVEL = 0 9
Thermal warning threshold (TDIE_WARN_LEVEL = 1) 127 137 147 °C Temperature rising, TDIE_WARN_LEVEL = 1 9
Thermal shutdown threshold 140 150 160 °C Temperature rising 9
VANA overvoltage threshold (rising) VANAOVP 5.6 5.8 6.1 V Voltage rising 9
VANA overvoltage threshold (falling) VANAOVP 5.45 5.73 5.96 V Voltage falling 9
VANA undervoltage lockout (rising) VANAUVLO 2.51 2.63 2.75 V Voltage rising 9
VANA undervoltage lockout (falling) VANAUVLO 2.5 2.6 2.7 V Voltage falling 9
Load current measurement accuracy 10 % IOUT > 1 A per phase; printed as <10% 9
Input current, all logic inputs ILEAK -1 1 µA All logic inputs over pin voltage range 11
Junction-to-ambient thermal resistance RθJA 36.7 °C/W 6
Junction-to-case (top) thermal resistance RθJCtop 26.6 °C/W 6
Junction-to-board thermal resistance RθJB 8.9 °C/W 6
Junction-to-case (bottom) thermal resistance RθJCbot 2.2 °C/W 6

CAD (KiCad official)

  • Symbol: LP873344RHDRQ1
  • Footprint: Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm
  • 3D model: VQFN-28(5x5) (KiCad packages3D, STEP)
  • 3D model files: lp873344rhdrq1-etched.step / lp873344rhdrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lp873344rhdrq1.step / lp873344rhdrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (87 pp, sha256 5c54b6621e0847f2, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF