LP6240SOF

{
  "slug": "lp6240sof",
  "version": "0.1.0",
  "type": "component",
  "description": "LOWPOWER DC-DC Converters, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "power management (pmic)",
    "lp6240sof",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "lp6240sof.kicad_sym",
    "lp6240sof.kicad_mod",
    "lp6240sof.glb",
    "lp6240sof.step",
    "lp6240sof.lbr",
    "docs/hero.png",
    "docs/lp6240sof-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "lp6240sof-hero.glb",
    "lp6240sof-hero.overlay.json"
  ],
  "component": {
    "mpn": "LP6240SOF",
    "manufacturer": "LOWPOWER",
    "package": "SOP-8",
    "pin_count": 8,
    "category": "Power Management (PMIC)",
    "subcategory": "DC-DC Converters",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884861683699712",
    "parts": {
      "symbol": "lp6240sof.kicad_sym",
      "footprint": "lp6240sof.kicad_mod",
      "model_3d": "lp6240sof-hero.glb",
      "model_3d_plain": "lp6240sof.glb",
      "model_3d_step": "lp6240sof-etched.step",
      "model_3d_step_plain": "lp6240sof.step",
      "lbr": "lp6240sof.lbr"
    },
    "distributor_links": {
      "lcsc": "C517062"
    },
    "distributor_check": {
      "checked_at": "2026-10-09T22:58:07Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "deferred",
        "error": "shared DigiKey quota guard: 540 calls left today"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VIN",
        "type": "power_in",
        "description": "Input supply pin; decouple with a 10μF ceramic capacitor close to the pin. Absolute maximum VIN to GND is −0.3V to +28V, and the input supply range is 4.5V to 24V."
      },
      {
        "number": "2",
        "name": "GATE",
        "type": "output",
        "description": "External N-channel MOSFET gate drive pin; the gate driver clamp is specified at 12V."
      },
      {
        "number": "3",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference pin."
      },
      {
        "number": "4",
        "name": "CS",
        "type": "input",
        "description": "Current sense input pin; CS, FB and COMP are rated −0.3V to +6.5V to GND in absolute maximum ratings."
      },
      {
        "number": "5",
        "name": "FB",
        "type": "input",
        "description": "Regulator feedback input, connected to an external resistive divider; the feedback voltage is 1.191V to 1.239V (1.215V typical)."
      },
      {
        "number": "6",
        "name": "COMP",
        "type": "passive",
        "description": "Regulator error amplifier compensation pin; CS, FB and COMP are rated −0.3V to +6.5V to GND in absolute maximum ratings."
      },
      {
        "number": "7",
        "name": "NC",
        "type": "unconnected",
        "description": "No connection."
      },
      {
        "number": "8",
        "name": "EN",
        "type": "input",
        "description": "Chip enable control; EN threshold is 1.5V minimum for logic high and 0.7V maximum for logic low, and GATE and EN are rated −0.3V to +28V to GND."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The Pin Configuration figure (page 2) is garbled in text extraction; pin numbers were taken from the; The datasheet is Preliminary (Version 0.1, May 2019). The order code LP6240SOF maps to the SO (SOP-8; The datasheet has no pin type designation for COMP or pin-level electrical limits beyond the absolut"
        ],
        "pages_sent": 6,
        "cost_usd": 0.03,
        "at": "2026-10-09T22:55:50"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884861683699712",
        "pages": 6,
        "sha256": "69056f38df50ee9c",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "lp6240sof.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-09",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "lp6240sof-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "8d7a59bd5fd286d9498bedc147b21946f4836ca59492dc48b61b95b2a4b6788c",
        "checked": "2026-10-09",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}