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LP6240SOF

Public Made by Adom

by adom

LOWPOWER DC-DC Converters, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 23d ago
viewers lp6240sof: viewers · Ray 23d ago
lp6240sof-etched.glb lp6240sof: factory component page (tier=lcsc) · Ray 23d ago
lp6240sof-etched.step lp6240sof: factory component page (tier=lcsc) · Ray 23d ago
lp6240sof-hero.glb lp6240sof: hero GLB from the etched model (keeps the MPN mark) · Ray 23d ago
lp6240sof-hero.overlay.json Publish 0.1.0 · Ray 23d ago
lp6240sof.glb Publish 0.1.0 · Ray 23d ago
lp6240sof.kicad_mod Publish 0.1.0 · Ray 23d ago
lp6240sof.kicad_sym Publish 0.1.0 · Ray 23d ago
lp6240sof.lbr Publish 0.1.0 · Ray 23d ago
lp6240sof.step Publish 0.1.0 · Ray 23d ago
package.json Publish 0.1.0 · Ray 23d ago
page.json lp6240sof: specified limits as data (metadata.characteristics, 36 rows from the datasheet) · Ray 17d ago
README.md lp6240sof: specified limits as data (metadata.characteristics, 36 rows from the datasheet) · Ray 17d ago

LP6240SOF

LOWPOWER · DC-DC Converters · SOP-8

LP6240SOF from LOWPOWER, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN power_in Input supply pin; decouple with a 10μF ceramic capacitor close to the pin. Absolute maximum VIN to GND is −0.3V to +28V, and the input supply range is 4.5V to 24V.
2 GATE output External N-channel MOSFET gate drive pin; the gate driver clamp is specified at 12V.
3 GND power_in Ground reference pin.
4 CS input Current sense input pin; CS, FB and COMP are rated −0.3V to +6.5V to GND in absolute maximum ratings.
5 FB input Regulator feedback input, connected to an external resistive divider; the feedback voltage is 1.191V to 1.239V (1.215V typical).
6 COMP passive Regulator error amplifier compensation pin; CS, FB and COMP are rated −0.3V to +6.5V to GND in absolute maximum ratings.
7 NC unconnected No connection.
8 EN input Chip enable control; EN threshold is 1.5V minimum for logic high and 0.7V maximum for logic low, and GATE and EN are rated −0.3V to +28V to GND.

Key specifications

Parameter Value
Manufacturer LOWPOWER
Package SOP-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Supply Voltage VIN 4.5 24 V 5
VIN Supply Current, Shutdown Current IQ 20 50 uA 5
VIN Supply Current, Sleep Current IQ 0.5 1 mA 5
VIN Supply Current, Operation Current IQ 2 4 mA 5
Feedback Voltage VFB 1.191 1.215 1.239 V 5
EN Threshold Voltage, Logic High VIH 1.5 V Logic High. 5
EN Threshold Voltage, Logic Low VIL 0.7 V Logic Low 5
Maximum Duty Cycle DMAX 80 % 5
VIN to GND -0.3 28 V 4
GATE, EN to GND -0.3 28 V 4
CS, FB, COMP to GND -0.3 6.5 V 4
Operating Junction Temperature Range TJ -40 150 ℃ 4
Operation Ambient Temperature Range -40 85 °C 4
Storage Temperature Range -65 150 °C 4
Maximum Soldering Temperature 260 °C at leads, 10sec 4
Maximum Junction Temperature 150 °C 4
Input UVLO Threshold VUVLO(VTH) 3.6 V VIN Rising 5
UVLO Threshold Hysteresis VUVLO(HYS) 170 mV Falling Hysteresis 5
Soft Start Time TSS 15 ms 5
Thermal Shutdown Threshold TSD 150 °C Temperature Rising 5
Thermal Shutdown Hysteresis ΔTSD 25 °C 5
Pull Down Resistor RPull_Low 150 kΩ 5
Internal Oscillator Frequency FOSC 600 kHz 5
Voltage Gain of Error Amplifier AV 1500 V/V 5
Transconductance of EA Gm 100 uA/V 5
Gate Driver Clamp 12 V 5
Gate rising time 40 uA CGate=500pF 5
Gate falling time 20 uA CGate=500pF 5
Over Current Protection Threshold VOCP 100 mV Threshold of OCP 5
Slope Compensation Current ISlope 40 uA 5
Under Voltage Protection VUVP 1 V 5
Fault Trigger Duration TFault 42 ms 5
SCP Threshold VSCP 0.5 V 5
Hiccup Off Timer 580 ms 5
Thermal Resistance, Junction to Ambient (SOP-8) θJA 112 °C/W 4
Thermal Resistance, Junction to Case (SOP-8) θJC 39 °C/W 4

CAD (KiCad official)

  • Symbol: LP6240SOF
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: lp6240sof-etched.step / lp6240sof-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lp6240sof.step / lp6240sof.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LOWPOWER datasheet (6 pp, sha256 69056f38df50ee9c, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF