hardware

LP5912Q1.1DRVRQ1 — Automotive 500 mA Low-Noise LDO, 1.1 V (TI)

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Texas Instruments LP5912-Q1 — AEC-Q100 grade-1 automotive 500-mA low-noise low-IQ LDO, fixed 1.1 V output. 1.6–6.5 V input, 12 µVRMS noise with no bypass capacitor, 75 dB PSRR at 1 kHz, 30 µA typical quiescent current, 170 mV typical dropout at 500 mA, open-drain power good, output auto-discharge and reverse-current protection, –40 to +125 °C junction, 6-pin WSON (DRV) 2.00 × 2.00 mm with exposed thermal pad.

componentldolinear-regulatorpowerlow-noiseautomotiveaec-q100texas-instrumentswsondrv1v1
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lp5912q1-1drvrq1 / skills / lp5912q1-1drvrq1-usage / SKILL.md
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name: lp5912q1-1drvrq1-usage description: > Use when adding a quiet 1.1 V (or other fixed-voltage LP5912-Q1) rail to a board, or when placing, wiring, thermally sizing or ordering the TI LP5912Q1.1DRVRQ1. Covers pin mapping, the input/output capacitors that keep it stable, EN and power-good wiring, exposed-pad and thermal layout for the WSON-6 (DRV) package, dropout and power-budget math, picking a different voltage option, and how to pull the symbol, footprint and 3D into KiCad or Fusion 360. Trigger words: LP5912, LP5912-Q1, LP5912Q1.1DRVRQ1, automotive LDO, AEC-Q100 regulator, 500 mA LDO, low noise LDO, low IQ LDO, 1.1 V rail, clean analog supply, PLL or SerDes core supply, power good pin, LDO thermal pad, C5220610, WSON-6 LDO. user-invocable: true

Parent skill: adom/lp5912q1-1drvrq1, the component page carrying the symbol, footprint, 3D, Fusion library and datasheet.

Using the LP5912Q1.1DRVRQ1

A 500 mA fixed-1.1 V LDO with 12 µVRMS noise and 30 µA quiescent current, AEC-Q100 grade 1. Use it where a switcher's ripple is unacceptable: PLL and VCO supplies, SerDes and PHY core rails, ADC/DAC analog supplies, image-sensor rails.

Pin mapping

Pin Name Connect to
6 IN the upstream rail, 1.6–6.5 V, with 1 µF ceramic to GND at the pin
1 OUT the load, with 1 µF ceramic to GND at the pin
4 EN a rail or a GPIO. Tie to IN for always-on; the internal 3 MΩ pulldown keeps it off if left floating
3 PG a pullup (10–100 kΩ) to whatever rail reads it, then a GPIO. Leave open if unused
5 GND ground plane
2 NC leave open, or tie to GND
7 EP ground copper under the package. Never to any other potential

The capacitors are not optional

Stability is specified with 1 µF ceramic on IN and 1 µF on OUT. What matters is the effective capacitance in-circuit: ≥ 0.5 µF must survive DC bias and temperature, so at 1.1 V a 1 µF X7R 0402/0603 is the safe pick. COUT may range 0.7–10 µF with 5–500 mΩ ESR. No noise-bypass capacitor is needed; that is the point of this part.

Dropout, thermals, and the power budget

Dropout at 500 mA is 170 mV typ / 250 mV max for output options below 3.3 V, so the input must stay above ~1.35 V for a full-current 1.1 V rail. In practice the input is a 3.3 V or 5 V rail, and then dissipation, not dropout, is the limit:

P = (VIN − 1.1 V) × IOUT

At 3.3 V in, 300 mA out that is 0.66 W. With RθJA = 71.2 °C/W (JEDEC high-K, two vias under the pad) the junction runs ~47 °C above ambient: fine at 85 °C ambient, marginal at 105 °C. Feed it from the lowest rail available, and if the drop is large, pre-regulate with a switcher and let the LP5912 clean up the result.

Thermal layout, in order of effect: solder the exposed pad to a ground pour, put at least two 0.2 mm vias in the pad into an inner ground layer, and give the pour room to spread on both sides of the board.

Enable and power good

  • EN thresholds are 1.3 V (on) and 0.3 V (off), so a 1.8 V or 3.3 V GPIO drives it directly. Turn-on is ~200 µs to 95% of VOUT, with internal soft-start and ≤5% overshoot. When EN goes low, a 100 Ω internal pulldown discharges OUT.
  • PG is open-drain: it releases high once VOUT passes 94% of nominal (with a 140 µs delay) and pulls low below 90%. It cannot source current, so without a pullup it reads as a floating input, not a logic high. Sequence downstream rails off this pin instead of guessing a delay.

Layout rules that matter

  1. Both capacitors at the pins. Loop area from IN/OUT through the cap to GND is what sets the real PSRR. Route GND from each cap to the pad's ground via, not across the pour.
  2. Exposed pad = thermal path, not a supply pin. It is internally tied to the die substrate; connect it to ground or leave it floating, never to VIN or VOUT.
  3. Small package. 2.00 × 2.00 mm body, 0.65 mm pitch, 0.35 × 0.60 mm pads on a 2.10 mm span, courtyard 3.20 × 2.60 mm. TI's example stencil is ~88% paste coverage on the exposed pad. If your assembler prints 100%, expect float on reflow.
  4. Keep OUT quiet. Do not run the 1.1 V rail under a switcher inductor; the low noise figure is a property of the part, not of the copper around it.

Picking another voltage

The DRV package is stocked at 0.9, 1.1, 1.2, 1.5, 1.8, 2.8, 3.0 and 3.3 V; the family covers 0.8–5.5 V in 25 mV steps to order. Same symbol, same footprint, same 3D, so swap the MPN in the BOM only. Options ≥ 3.3 V tighten to ±2% and 95 mV typ dropout; this 1.1 V option is ±3%.

Getting the CAD in

adom-wiki pkg install adom/lp5912q1-1drvrq1   # symbol + footprint + STEP + GLB + .lbr
  • KiCad: add LP5912Q1_1DRVRQ1.kicad_sym to sym-lib-table and the directory holding SON65P200X200X80-7N.kicad_mod to fp-lib-table, both as the nickname LP5912Q1_1DRVRQ1. The symbol's Footprint field already reads LP5912Q1_1DRVRQ1:SON65P200X200X80-7N, and the footprint points at lp5912q1-1drvrq1.step for the 3D viewer.
  • Fusion 360 Electronics: open LP5912Q1_1DRVRQ1.lbr directly. It carries the symbol, the package, and a complete deviceset.
  • Altium: adom-lbr export-altium lp5912q1-1drvrq1.adom-lbr.json for .SchLib + .PcbLib, or export-intlib for one .IntLib.

Ordering

Mouser 595-LP5912Q1.1DRVRQ1, DigiKey 296-46972-2-ND, LCSC C5220610. The DRVR suffix is the 3000-piece reel; the DRVT (250-piece) variants of this family are obsolete, so specify DRVR. Part marking on the package is 12QH.