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LP0701LG-G

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Microchip Tech MOSFETs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LP0701LG-G

Microchip Tech · MOSFETs · SOIC-8

LP0701LG-G from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No connection; this pin is not connected internally and is listed as NC in the 8-lead SOIC pin function table.
2 NC unconnected No connection; this pin is not connected internally and is listed as NC in the 8-lead SOIC pin function table.
3 Source passive Source terminal of the P-channel enhancement-mode lateral MOSFET; the datasheet gives no pin-specific electrical limit for this terminal.
4 Gate input Gate terminal of the MOSFET; the absolute maximum gate-to-source voltage is ±10V.
5 Drain passive Drain terminal of the MOSFET; the drain-to-source breakdown voltage BVDSS is -16.5V minimum at VGS = 0V and ID = -1 mA.
6 Drain passive Drain terminal of the MOSFET; the drain-to-source breakdown voltage BVDSS is -16.5V minimum at VGS = 0V and ID = -1 mA.
7 Drain passive Drain terminal of the MOSFET; the drain-to-source breakdown voltage BVDSS is -16.5V minimum at VGS = 0V and ID = -1 mA.
8 Drain passive Drain terminal of the MOSFET; the drain-to-source breakdown voltage BVDSS is -16.5V minimum at VGS = 0V and ID = -1 mA.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-8
Category Triode/MOS Tube/Transistor
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Gate-to-Source Voltage VGS -10 10 V 2
Operating Ambient Temperature TA -55 150 °C 2
Storage Temperature TS -55 150 °C 2
Operating Ambient Temperature TA -55 150 °C 3
Storage Temperature TS -55 150 °C 3
Gate Threshold Voltage VGS(th) -0.5 -0.7 -1 V VGS = VDS, ID = -1 mA 2
Change in VGS(th) with Temperature ∆VGS(th) -4 mV/°C VGS = VDS, ID = -1 mA (Note 1) 2
Gate Body Leakage Current IGSS -100 nA VGS = ±10V, VDS = 0V 2
Zero-Gate Voltage Drain Current IDSS -100 nA VDS = -15V, VGS = 0V 2
Zero-Gate Voltage Drain Current IDSS -1 mA VDS = 0.8 Maximum rating, VGS = 0V, TA= 125°C (Note 1) 2
On-State Drain Current ID(ON) -0.6 -1 A VGS = VDS = -3V 2
On-State Drain Current ID(ON) -1.25 -2.3 A VGS = VDS = -5V 2
Static Drain-to-Source On-State Resistance RDS(ON) 2 4 Ω VGS = -2V, ID = -50 mA 2
Static Drain-to-Source On-State Resistance RDS(ON) 1.7 2 Ω VGS = -3V, ID = -150 mA 2
Static Drain-to-Source On-State Resistance RDS(ON) 1.3 1.5 Ω VGS = -5V, ID = -300 mA 2
Change in RDS(ON) with Temperature ∆RDS(ON) 0.75 %/°C VGS = -5V, ID = -300 mA (Note 1) 2
Drain-to-Source Breakdown Voltage BVDSS -16.5 V VGS = 0V, ID = -1 mA 2
Forward Transconductance GFS 500 700 mmho VGS = -15V, ID = -1A 3
Input Capacitance CISS 120 250 pF VGS = 0V, VDS = -15V, f = 1 MHz 3
Common Source Output Capacitance COSS 100 125 pF 3
Reverse Transfer Capacitance CRSS 40 60 pF 3
Turn-On Delay Time td(ON) 20 ns VDD = -15V, ID = -1.25A, RGEN = 25Ω 3
Rise Time tr 20 ns VDD = -15V, ID = -1.25A, RGEN = 25Ω 3
Turn-Off Delay Time td(OFF) 30 ns VDD = -15V, ID = -1.25A, RGEN = 25Ω 3
Fall Time tf 30 ns VDD = -15V, ID = -1.25A, RGEN = 25Ω 3
Diode Forward Voltage Drop VSD -1.2 -1.5 V VGS = 0V, ISD = -500 mA (Note 1) 3
Continuous Drain Current, 8-lead SOIC ID -700 mA Continuous; limited by maximum rated TJ (Note 1) 3
Pulsed Drain Current, 8-lead SOIC ID -1.25 A Pulsed 3
Power Dissipation, 8-lead SOIC PD 1.5 W TA = 25°C (Note 2) 3
Reverse Drain Current, 8-lead SOIC IDR -700 mA (Note 1) 3
Reverse Drain Pulsed Current, 8-lead SOIC IDRM -1.25 A 3
Junction-to-Ambient Thermal Resistance, 8-lead SOIC θJA 101 °C/W Mounted on FR4 board, 25 mm x 25 mm x 1.57 mm (Note 1) 3

CAD (KiCad official)

  • Symbol: LP0701LG-G
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: lp0701lg-g-etched.step / lp0701lg-g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lp0701lg-g.step / lp0701lg-g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (14 pp, sha256 3da64875eafd8779, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF