component
LMR50410Y5FQDBVRQ1
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownLMR50410Y5FQDBVRQ1
Texas Instruments · DC-DC Converters · SOT-23-6
LMR50410Y5FQDBVRQ1 from Texas Instruments, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CB | passive | Bootstrap capacitor connection for the high-side FET driver; connect a high quality 100-nF capacitor from this pin to the SW pin (CB to SW max 5.5 V). |
| 2 | GND | power_in | Power ground terminal connected to the source of the low-side FET internally; connect to system ground and the ground side of CIN and COUT, with the path to CIN as short as possible. |
| 3 | FB | input | Feedback input to the converter; for this fixed 5.0-V output version connect it directly to the output point, and never short it to ground during operation (FB to GND max 5.5 V). |
| 4 | EN | input | Precision enable input (high = on, low = off) that must not be floated, can be tied to VIN, and allows adjustable UVLO with an external resistor divider. |
| 5 | VIN | power_in | Supply input terminal to the internal bias LDO and high-side FET, operating range 4 V to 36 V, with input bypass capacitors CIN connected directly between this pin and GND. |
| 6 | SW | passive | Switching output of the converter, internally connected to the source of the high-side FET and drain of the low-side FET; connect to the power inductor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-6 |
| Category | Power Supply Chip |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Rising UVLO threshold | VIN_UVLO | 3.55 | 3.75 | 4 | V | Rising threshold | 5 |
| Falling UVLO threshold | VIN_UVLO | 3.25 | 3.45 | 3.65 | V | Falling threshold | 5 |
| Shutdown quiescent current | ISD | 3 | 10 | µA | VEN = 0 V | 5 | |
| Enable input high-level | VEN-VOUT-H | 1.1 | 1.23 | 1.36 | V | VENABLE rising | 5 |
| Enable input low-level | VEN-VOUT-L | 0.95 | 1.1 | 1.22 | V | VENABLE falling | 5 |
| Enable input leakage current | ILKG-EN | 10 | 200 | nA | VEN = 3.3V | 5 | |
| Output voltage (5 V fixed) | VOUT-5V-Fixed | 4.925 | 5 | 5.075 | V | Vin=12V | 5 |
| High-side current limit | ISC | 1.25 | 1.6 | 1.9 | A | Vin=12V | 5 |
| Low-side current limit | ILS-LIMIT | 0.9 | 1.1 | 1.3 | A | Vin=12V | 5 |
| Internal oscillator frequency | FOSC | 1.8 | 2.1 | 2.4 | MHz | 2.1-MHz variant | 6 |
| Input voltage VIN to GND (abs max) | VIN | -0.3 | 38 | V | VIN to GND | 4 | |
| EN to GND (abs max) | EN | -0.3 | V | Max is VIN+0.3 | 4 | ||
| FB to GND (abs max) | FB | -0.3 | 5.5 | V | FB to GND | 4 | |
| SW to GND (abs max) | SW | -0.3 | V | Max is VIN+0.3 | 4 | ||
| SW to GND transients | SW | -3.5 | 38 | V | less than 10-ns transients | 4 | |
| CB to SW (abs max) | CB | -0.3 | 5.5 | V | CB to SW | 4 | |
| Junction temperature (abs max) | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| ESD HBM | V(ESD) | -2500 | 2500 | V | Human body model (HBM) | 4 | |
| ESD CDM | V(ESD) | -750 | 750 | V | Charged device model (CDM) | 4 | |
| Input voltage VIN to GND | VIN | 4 | 36 | V | VIN to GND | 4 | |
| EN to GND | EN | 0 | V | Max is VIN | 4 | ||
| Output current | IOUT | 0 | 1 | A | 4 | ||
| Junction-to-ambient thermal resistance | RθJA | 173 | °C/W | DBV (SOT-23-6) | 4 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 116 | °C/W | DBV (SOT-23-6) | 4 | ||
| Junction-to-board thermal resistance | RθJB | 31 | °C/W | DBV (SOT-23-6) | 4 | ||
| Junction-to-top characterization parameter | ψJT | 20 | °C/W | DBV (SOT-23-6) | 4 | ||
| Junction-to-board characterization parameter | ψJB | 30 | °C/W | DBV (SOT-23-6) | 5 | ||
| Negative current limit | IL-NEG | -0.6 | A | FPWM variant only | 5 | ||
| High-side MOSFET ON-resistance | RDS-ON-HS | 450 | mΩ | TJ=25 ℃, VIN = 12 V | 5 | ||
| Low-side MOSFET ON-resistance | RDS-ON-LS | 240 | mΩ | TJ=25 ℃, VIN = 12 V | 5 | ||
| Thermal shutdown threshold | TSD-Rising | 170 | °C | Shutdown threshold | 5 | ||
| Thermal shutdown recovery threshold | TSD-Falling | 158 | °C | Recovery threshold | 6 | ||
| Feedback leakage current (5 V fixed) | ILKG-VOUT-5V-Fixed | 2.6 | µA | VOUT = 5V (Fixed Option) | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | The SW pin connecting to the inductor must be as short as possible, and just wide enough to carry the load current without excessive heating. Short, thick traces or copper pours (shapes) must be used | 27 |
CAD (KiCad official)
- Symbol:
LMR50410Y5FQDBVRQ1 - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
lmr50410y5fqdbvrq1-etched.step/lmr50410y5fqdbvrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lmr50410y5fqdbvrq1.step/lmr50410y5fqdbvrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (38 pp, sha256
70125484c2028d37, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).