component

LMR33640DDDAR

Public Made by Adom

by adom

Texas Instruments DC-DC Converters, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)lmr33640dddarfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

LMR33640DDDAR

Texas Instruments · DC-DC Converters · SOIC-8-EP

LMR33640DDDAR from Texas Instruments, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PGND power_in Power ground terminal; connect to system ground, AGND, and bypass capacitor with short wide traces.
2 VIN power_in Regulator input supply operating from 3.8 V to 36 V; connect high-quality bypass capacitors directly to this pin and PGND.
3 EN input Enable control input with rising threshold of 1.26 V enabling switching and falling threshold of 0.3 V disabling device; do not float.
4 PG tri_state Open-drain power-good output indicating regulation status with upper threshold at 107% of FB and lower at 94% of FB; pulls low on fault or during soft start.
5 FB input Feedback input connected to output voltage divider tap point with nominal reference voltage of 1 V; do not float or ground.
6 VCC power_out Internal 5-V LDO output regulated from 4.75 V to 5.25 V supplying internal control circuits; connect 1-µF capacitor to PGND and do not load externally.
7 BOOT power_out Bootstrap supply for internal high-side gate driver with minimum undervoltage threshold of 2.2 V; connect 100-nF capacitor from this pin to SW.
8 SW output Switching node driven by internal MOSFETs with voltage rating from -0.3 V to 38 V, supporting transients to -3.5 V under 100 ns; connect to power inductor.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8-EP
Category Power Management (PMIC)
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN to PGND -0.3 38 V 5
EN to AGND (max printed as VIN + 0.3) -0.3 V 5
FB to AGND -0.3 5.5 V 5
PG to AGND 0 22 V 5
AGND to PGND -0.3 0.3 V 5
SW to PGND (max printed as VIN + 0.3) -0.3 V 5
SW to PGND less than 100-ns transients -3.5 38 V less than 100-ns transients 5
BOOT to SW -0.3 5.5 V 5
VCC to AGND -0.3 5.5 V 5
Junction temperature TJ -40 150 °C 5
Storage temperature Tstg -55 150 °C 5
VIN to PGND (recommended operating input voltage) 3.8 36 V 5
EN (max printed as VIN) 0 V 5
PG 0 18 V 5
Adjustable output voltage VOUT 1 24 V 5
Output current IOUT 0 4 A 5
Minimum operating input voltage VIN 3.8 V 6
Non-switching input current, measured at VIN pin IQ 24 34 µA VFB = 1.2 V 6
Shutdown quiescent current, measured at VIN pin ISD 5 10 µA EN = 0 V 6
EN input level required to start switching (rising threshold) VEN-H 1.2 1.231 1.26 V Rising threshold 6
Internal LDO output voltage at VCC pin VCC 4.75 5 5.25 V 6 V ≤ VIN ≤ 36 V 6
Feedback voltage; ADJ option VFB 0.985 1 1.015 V ADJ option 6
Current into FB pin; ADJ option IFB 0.2 50 nA ADJ option, FB = 1 V 6
High-side current limit ISC 4.8 5.5 6.2 A LMR33640 6
Low-side current limit ILIMIT 3.9 4.5 5 A LMR33640 6
Internal soft-start time tSS 2.9 4 6 ms 7
Power-good upper threshold, rising VPG-HIGH-UP 105 107 110 % % of FB voltage, rising 7
Power-good upper threshold, falling VPG-HIGH-DN 103 105 108 % % of FB voltage, falling 7
Power-good lower threshold, rising VPG-LOW-UP 92 94 97 % % of FB voltage, rising 7
Power-good lower threshold, falling VPG-LOW-DN 90 92 95 % % of FB voltage, falling 7
Power-good glitch filter delay tPG 60 170 µs 7
Power-good flag RDSON RPG 76 150 Ω VIN = 12 V, VEN = 4 V 7
Power-good flag RDSON RPG 35 60 Ω VEN = 0 V 7
Minimum input voltage for proper PG function VIN-PG 2 V 50-µA, EN = 0 V 7
PG logic low output VPG 0.2 V 50-µA, EN = 0 V, VIN = 2V 7
Switching frequency (DDDA 1000 kHz option) ƒSW 860 1000 1140 kHz 7
High-side MOSFET ON-resistance, DDA package RDS-ON-HS 95 160 mΩ DDA package 7
Low-side MOSFET ON-resistance, DDA package RDS-ON-LS 66 110 mΩ DDA package 7
Minimum switch on-time, DDA package tON-MIN 75 108 ns DDA package 7
Minimum switch off-time, DDA package tOFF-MIN 50 85 ns DDA package 7
Maximum switch on-time tON-MAX 7 9 µs 7
Output voltage regulation for VOUT = 5 V VOUT -1.6 2.5 % VOUT = 5 V, VIN = 7 V to 36 V, IOUT = 0 A to 4 A 8
Output voltage regulation for VOUT = 5 V VOUT -1.6 1.5 % VOUT = 5 V, VIN = 7 V to 36 V, IOUT = 1 A to 4 A 8
Output voltage regulation for VOUT = 3.3 V VOUT -1.6 2.5 % VOUT = 3.3 V, VIN = 3.8 V to 36 V, IOUT = 0 A to 4 A 8
Output voltage regulation for VOUT = 3.3 V VOUT -1.6 1.5 % VOUT = 3.3 V, VIN = 3.8 V to 36 V, IOUT = 1 A to 4 A 8
EN input level required to turn on internal LDO (rising threshold) VEN-VCC-H 1 V Rising threshold 6
EN input level required to turn off internal LDO (falling threshold) VEN-VCC-L 0.3 V Falling threshold 6
Hysteresis below VEN-H VEN-HYS 100 mV Hysteresis below VEN-H; falling 6
Enable input leakage current ILKG-EN 0.2 nA VEN = 3.3 V 6
Bootstrap voltage undervoltage lock-out threshold VBOOT-UVLO 2.2 V 6
Minimum peak inductor current IPEAK-MIN 0.824 A LMR33640 6
Zero current detector threshold IZC -0.106 A 7
Input supply current when in regulation ISUPPLY 25 µA VIN = 12 V, VOUT = 3.3 V, IOUT = 0 A, RFBT = 1 MΩ 8
Dropout voltage; (VIN – VOUT) VDROP 150 mV VOUT = 5 V, IOUT = 1A; dropout at -1% of regulation, fSW = 140 kHz 8
Maximum switch duty cycle DMAX 98 % VIN = VOUT = 12 V, IOUT = 1 A 8
FB pin voltage required to trip short-circuit hiccup mode VHC 0.4 V 8
Thermal shutdown temperature (shutdown) TSD 165 °C Shutdown temperature 8
Junction-to-ambient thermal resistance, DDA (HSOIC) RθJA 42.9 °C/W JESD 51-7, 4-layer JEDEC board; not valid for design 6
Junction-to-board thermal resistance, DDA (HSOIC) RθJB 13.6 °C/W 6
Junction-to-case (bottom) thermal resistance, DDA (HSOIC) RθJC(bot) 4.3 °C/W 6

CAD (KiCad official)

  • Symbol: LMR33640DDDAR
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: SOIC-8-EP (KiCad packages3D, STEP)
  • 3D model files: lmr33640dddar-etched.step / lmr33640dddar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmr33640dddar.step / lmr33640dddar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (44 pp, sha256 6df39cb52faaed45, retrieved 2026-09-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF