LMK04228NKDR

{
  "slug": "lmk04228nkdr",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Clock Generators / Frequency Synthesizers / PLL, WQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "rtc-clock chip",
    "lmk04228nkdr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "lmk04228nkdr.kicad_sym",
    "lmk04228nkdr.kicad_mod",
    "lmk04228nkdr.glb",
    "lmk04228nkdr.step",
    "lmk04228nkdr.lbr",
    "docs/hero.png",
    "docs/lmk04228nkdr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "lmk04228nkdr-hero.glb",
    "lmk04228nkdr-hero.overlay.json"
  ],
  "component": {
    "mpn": "LMK04228NKDR",
    "manufacturer": "Texas Instruments",
    "package": "WQFN-64-EP(9x9)",
    "pin_count": 65,
    "category": "RTC/Clock Chip",
    "subcategory": "Clock Generators / Frequency Synthesizers / PLL",
    "datasheet": "https://www.ti.com/cn/lit/gpn/lmk04228",
    "parts": {
      "symbol": "lmk04228nkdr.kicad_sym",
      "footprint": "lmk04228nkdr.kicad_mod",
      "model_3d": "lmk04228nkdr-hero.glb",
      "model_3d_plain": "lmk04228nkdr.glb",
      "model_3d_step": "lmk04228nkdr-etched.step",
      "model_3d_step_plain": "lmk04228nkdr.step",
      "lbr": "lmk04228nkdr.lbr"
    },
    "distributor_links": {
      "lcsc": "C1849247",
      "digikey": "296-LMK04228NKDRTR-ND",
      "mouser": "595-LMK04228NKDR"
    },
    "distributor_check": {
      "checked_at": "2026-10-08T22:11:43Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-LMK04228NKDRTR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "595-LMK04228NKDR",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "DCLKout0",
        "type": "output",
        "description": "Programmable device clock output 0 (differential true output of the DCLKout0 pair)."
      },
      {
        "number": "2",
        "name": "DCLKout0*",
        "type": "output",
        "description": "Complementary half of the DCLKout0 differential output pair, as listed with 'Programmable Device clock output 0'."
      },
      {
        "number": "3",
        "name": "SDCLKout1",
        "type": "output",
        "description": "Programmable SYSREF / device clock output 1 (true output)."
      },
      {
        "number": "4",
        "name": "SDCLKout1*",
        "type": "output",
        "description": "Complementary half of the SDCLKout1 differential output pair, as listed with 'Programmable SYSREF / Device clock output 1'."
      },
      {
        "number": "5",
        "name": "RESET/GPO",
        "type": "input",
        "description": "Device reset input or general-purpose output (GPO); CMOS levels."
      },
      {
        "number": "6",
        "name": "SYNC/SYSREF_REQ",
        "type": "input",
        "description": "CMOS synchronization input, or SYSREF_REQ for requesting continuous SYSREF."
      },
      {
        "number": "7",
        "name": "NC",
        "type": "unconnected",
        "description": "Do not connect; this pin must be left floating."
      },
      {
        "number": "8",
        "name": "NC",
        "type": "unconnected",
        "description": "Do not connect; this pin must be left floating."
      },
      {
        "number": "9",
        "name": "NC",
        "type": "unconnected",
        "description": "Do not connect; this pin must be left floating."
      },
      {
        "number": "10",
        "name": "Vcc1_VCO",
        "type": "power_in",
        "description": "Power supply for the VCO LDO."
      },
      {
        "number": "11",
        "name": "LDObyp1",
        "type": "passive",
        "description": "LDO bypass pin, bypassed to ground with a 10-µF capacitor."
      },
      {
        "number": "12",
        "name": "LDObyp2",
        "type": "passive",
        "description": "LDO bypass pin, bypassed to ground with a 0.1-µF capacitor."
      },
      {
        "number": "13",
        "name": "SDCLKout3",
        "type": "output",
        "description": "Programmable SYSREF / device clock output 3 (true output)."
      },
      {
        "number": "14",
        "name": "SDCLKout3*",
        "type": "output",
        "description": "Complementary half of the SDCLKout3 differential output pair, as listed with 'Programmable SYSREF / Device Clock output 3'."
      },
      {
        "number": "15",
        "name": "DCLKout2",
        "type": "output",
        "description": "Programmable device clock output 2 (true output)."
      },
      {
        "number": "16",
        "name": "DCLKout2*",
        "type": "output",
        "description": "Complementary half of the DCLKout2 differential output pair, as listed with 'Programmable Device clock output 2'."
      },
      {
        "number": "17",
        "name": "Vcc2_CG1",
        "type": "power_in",
        "description": "Power supply for clock outputs 2 and 3."
      },
      {
        "number": "18",
        "name": "CS*",
        "type": "input",
        "description": "SPI chip select input, CMOS."
      },
      {
        "number": "19",
        "name": "SCK",
        "type": "input",
        "description": "SPI clock input, CMOS."
      },
      {
        "number": "20",
        "name": "SDIO",
        "type": "bidirectional",
        "description": "SPI data input/output, CMOS."
      },
      {
        "number": "21",
        "name": "Vcc3_SYSREF",
        "type": "power_in",
        "description": "Power supply for the SYSREF divider and SYNC."
      },
      {
        "number": "22",
        "name": "SDCLKout5",
        "type": "output",
        "description": "Programmable SYSREF / device clock output 5 (true output)."
      },
      {
        "number": "23",
        "name": "SDCLKout5*",
        "type": "output",
        "description": "Complementary half of the SDCLKout5 differential output pair; the datasheet prints this name as 'SDCKLout5*'."
      },
      {
        "number": "24",
        "name": "DCLKout4",
        "type": "output",
        "description": "Programmable device clock output 4 (true output)."
      },
      {
        "number": "25",
        "name": "DCLKout4*",
        "type": "output",
        "description": "Complementary half of the DCLKout4 differential output pair, as listed with 'Programmable Device clock output 4'."
      },
      {
        "number": "26",
        "name": "Vcc4_CG2",
        "type": "power_in",
        "description": "Power supply for clock outputs 4, 5, 6 and 7."
      },
      {
        "number": "27",
        "name": "DCLKout6",
        "type": "output",
        "description": "Programmable device clock output 6 (true output)."
      },
      {
        "number": "28",
        "name": "DCLKout6*",
        "type": "output",
        "description": "Complementary half of the DCLKout6 differential output pair, as listed with 'Programmable Device clock output 6'."
      },
      {
        "number": "29",
        "name": "SDCLKout7",
        "type": "output",
        "description": "Programmable SYSREF / device clock output 7 (true output)."
      },
      {
        "number": "30",
        "name": "SDCLKout7*",
        "type": "output",
        "description": "Complementary half of the SDCLKout7 differential output pair, as listed with 'Programmable SYSREF / Device clock output 7'."
      },
      {
        "number": "31",
        "name": "Status_LD1",
        "type": "bidirectional",
        "description": "Programmable status pin (I/O, CMOS)."
      },
      {
        "number": "32",
        "name": "CPout1",
        "type": "output",
        "description": "Charge pump 1 output (analog) for PLL1."
      },
      {
        "number": "33",
        "name": "Vcc5_DIG",
        "type": "power_in",
        "description": "Power supply for the digital circuitry."
      },
      {
        "number": "34",
        "name": "CLKin1",
        "type": "input",
        "description": "Reference clock input port 1 for PLL1 (analog, true input)."
      },
      {
        "number": "35",
        "name": "CLKin1*",
        "type": "input",
        "description": "Complementary reference clock input port 1 for PLL1; AC-couple per the clock input specifications."
      },
      {
        "number": "36",
        "name": "Vcc6_PLL1",
        "type": "power_in",
        "description": "Power supply for PLL1, charge pump 1 and holdover DAC."
      },
      {
        "number": "37",
        "name": "CLKin0",
        "type": "input",
        "description": "Reference clock input port 0 for PLL1 (analog, true input)."
      },
      {
        "number": "38",
        "name": "CLKin0*",
        "type": "input",
        "description": "Complementary reference clock input port 0 for PLL1 (analog)."
      },
      {
        "number": "39",
        "name": "Vcc7_OSCout",
        "type": "power_in",
        "description": "Power supply for the OSCout port."
      },
      {
        "number": "40",
        "name": "OSCout/CLKin2",
        "type": "output",
        "description": "Programmable buffered output of the OSCin port; the datasheet notes OSCout may also be the third clock input, CLKin2."
      },
      {
        "number": "41",
        "name": "OSCout*/CLKin2*",
        "type": "input",
        "description": "Complementary reference clock input port 2 for PLL1 (CLKin2*), shared with the complementary OSCout output."
      },
      {
        "number": "42",
        "name": "Vcc8_OSCin",
        "type": "power_in",
        "description": "Power supply for OSCin."
      },
      {
        "number": "43",
        "name": "OSCin",
        "type": "input",
        "description": "Feedback to PLL1 and reference input to PLL2; AC-coupled (analog)."
      },
      {
        "number": "44",
        "name": "OSCin*",
        "type": "input",
        "description": "Complementary OSCin input; AC-coupled (analog) feedback to PLL1 and reference to PLL2."
      },
      {
        "number": "45",
        "name": "Vcc9_CP2",
        "type": "power_in",
        "description": "Power supply for the PLL2 charge pump."
      },
      {
        "number": "46",
        "name": "CPout2",
        "type": "output",
        "description": "Charge pump 2 output (analog) for PLL2."
      },
      {
        "number": "47",
        "name": "Vcc10_PLL2",
        "type": "power_in",
        "description": "Power supply for PLL2."
      },
      {
        "number": "48",
        "name": "Status_LD2",
        "type": "bidirectional",
        "description": "Programmable status pin (I/O, programmable)."
      },
      {
        "number": "49",
        "name": "SDCLKout9",
        "type": "output",
        "description": "Programmable SYSREF / device clock output 9 (true output)."
      },
      {
        "number": "50",
        "name": "SDCLKout9*",
        "type": "output",
        "description": "Complementary half of the SDCLKout9 differential output pair, as listed with 'Programmable SYSREF / Device clock 9'."
      },
      {
        "number": "51",
        "name": "DCLKout8",
        "type": "output",
        "description": "Programmable device clock output 8 (true output)."
      },
      {
        "number": "52",
        "name": "DCLKout8*",
        "type": "output",
        "description": "Complementary half of the DCLKout8 differential output pair, as listed with 'Programmable Device clock output 8'."
      },
      {
        "number": "53",
        "name": "Vcc11_CG3",
        "type": "power_in",
        "description": "Power supply for clock outputs 8, 9, 10 and 11."
      },
      {
        "number": "54",
        "name": "DCLKout10",
        "type": "output",
        "description": "Programmable device clock output 10 (true output)."
      },
      {
        "number": "55",
        "name": "DCLKout10*",
        "type": "output",
        "description": "Complementary half of the DCLKout10 differential output pair, as listed with 'Programmable Device clock output 10'."
      },
      {
        "number": "56",
        "name": "SDCLKout11",
        "type": "output",
        "description": "Programmable SYSREF / device clock output 11 (true output)."
      },
      {
        "number": "57",
        "name": "SDCLKout11*",
        "type": "output",
        "description": "Complementary half of the SDCLKout11 differential output pair, as listed with 'Programmable SYSREF / Device clock output 11'."
      },
      {
        "number": "58",
        "name": "CLKin_SEL0",
        "type": "bidirectional",
        "description": "Programmable status pin (I/O) used for clock input selection."
      },
      {
        "number": "59",
        "name": "CLKin_SEL1",
        "type": "bidirectional",
        "description": "Programmable status pin (I/O) used for clock input selection."
      },
      {
        "number": "60",
        "name": "SDCLKout13",
        "type": "output",
        "description": "Programmable SYSREF / device clock output 13 (true output)."
      },
      {
        "number": "61",
        "name": "SDCLKout13*",
        "type": "output",
        "description": "Complementary half of the SDCLKout13 differential output pair, as listed with 'Programmable SYSREF / Device clock output 13'."
      },
      {
        "number": "62",
        "name": "DCLKout12",
        "type": "output",
        "description": "Programmable device clock output 12 (true output)."
      },
      {
        "number": "63",
        "name": "DCLKout12*",
        "type": "output",
        "description": "Complementary half of the DCLKout12 differential output pair, as listed with 'Programmable Device clock output 12'."
      },
      {
        "number": "64",
        "name": "Vcc12_CG0",
        "type": "power_in",
        "description": "Power supply for clock outputs 0, 1, 12 and 13."
      },
      {
        "number": "65",
        "name": "DAP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The exposed die attach pad (DAP, labeled 'GND DIE ATTACH PAD, connect to GND' on page 6) has no prin; Pin 41 has no I/O type in the Pin Functions table; only its description ('Reference Clock Input Port; Pins 7, 8 and 9 are printed as one NC row ('7, 8, 9 NC'); each is listed separately with the same de",
          "exposed pad 65 added from the footprint"
        ],
        "pages_sent": 14,
        "cost_usd": 0.12,
        "at": "2026-10-08T22:10:46"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/lmk04228",
        "pages": 89,
        "sha256": "3217c7afebcd700e",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 65,
        "described": 65,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "lmk04228nkdr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          9.0,
          9.0,
          0.75
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "dce07a86ec3fe3ca87eebdff13827f55e036ced5518fee01f85cec4a3f56366d",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "lmk04228nkdr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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          9.0,
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        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3c1eb3c4f2ecc1199b639c1ce36c50f25acf2bda36fa152711ebb7820e26aa9a",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}