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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

LMK04228NKDR

Texas Instruments · Clock Generators / Frequency Synthesizers / PLL · WQFN-64-EP(9x9)

LMK04228NKDR from Texas Instruments, in a WQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DCLKout0	output	Programmable device clock output 0 (differential true output of the DCLKout0 pair).
2	DCLKout0*	output	Complementary half of the DCLKout0 differential output pair, as listed with 'Programmable Device clock output 0'.
3	SDCLKout1	output	Programmable SYSREF / device clock output 1 (true output).
4	SDCLKout1*	output	Complementary half of the SDCLKout1 differential output pair, as listed with 'Programmable SYSREF / Device clock output 1'.
5	RESET/GPO	input	Device reset input or general-purpose output (GPO); CMOS levels.
6	SYNC/SYSREF_REQ	input	CMOS synchronization input, or SYSREF_REQ for requesting continuous SYSREF.
7	NC	unconnected	Do not connect; this pin must be left floating.
8	NC	unconnected	Do not connect; this pin must be left floating.
9	NC	unconnected	Do not connect; this pin must be left floating.
10	Vcc1_VCO	power_in	Power supply for the VCO LDO.
11	LDObyp1	passive	LDO bypass pin, bypassed to ground with a 10-µF capacitor.
12	LDObyp2	passive	LDO bypass pin, bypassed to ground with a 0.1-µF capacitor.
13	SDCLKout3	output	Programmable SYSREF / device clock output 3 (true output).
14	SDCLKout3*	output	Complementary half of the SDCLKout3 differential output pair, as listed with 'Programmable SYSREF / Device Clock output 3'.
15	DCLKout2	output	Programmable device clock output 2 (true output).
16	DCLKout2*	output	Complementary half of the DCLKout2 differential output pair, as listed with 'Programmable Device clock output 2'.
17	Vcc2_CG1	power_in	Power supply for clock outputs 2 and 3.
18	CS*	input	SPI chip select input, CMOS.
19	SCK	input	SPI clock input, CMOS.
20	SDIO	bidirectional	SPI data input/output, CMOS.
21	Vcc3_SYSREF	power_in	Power supply for the SYSREF divider and SYNC.
22	SDCLKout5	output	Programmable SYSREF / device clock output 5 (true output).
23	SDCLKout5*	output	Complementary half of the SDCLKout5 differential output pair; the datasheet prints this name as 'SDCKLout5*'.
24	DCLKout4	output	Programmable device clock output 4 (true output).
25	DCLKout4*	output	Complementary half of the DCLKout4 differential output pair, as listed with 'Programmable Device clock output 4'.
26	Vcc4_CG2	power_in	Power supply for clock outputs 4, 5, 6 and 7.
27	DCLKout6	output	Programmable device clock output 6 (true output).
28	DCLKout6*	output	Complementary half of the DCLKout6 differential output pair, as listed with 'Programmable Device clock output 6'.
29	SDCLKout7	output	Programmable SYSREF / device clock output 7 (true output).
30	SDCLKout7*	output	Complementary half of the SDCLKout7 differential output pair, as listed with 'Programmable SYSREF / Device clock output 7'.
31	Status_LD1	bidirectional	Programmable status pin (I/O, CMOS).
32	CPout1	output	Charge pump 1 output (analog) for PLL1.
33	Vcc5_DIG	power_in	Power supply for the digital circuitry.
34	CLKin1	input	Reference clock input port 1 for PLL1 (analog, true input).
35	CLKin1*	input	Complementary reference clock input port 1 for PLL1; AC-couple per the clock input specifications.
36	Vcc6_PLL1	power_in	Power supply for PLL1, charge pump 1 and holdover DAC.
37	CLKin0	input	Reference clock input port 0 for PLL1 (analog, true input).
38	CLKin0*	input	Complementary reference clock input port 0 for PLL1 (analog).
39	Vcc7_OSCout	power_in	Power supply for the OSCout port.
40	OSCout/CLKin2	output	Programmable buffered output of the OSCin port; the datasheet notes OSCout may also be the third clock input, CLKin2.
41	OSCout/CLKin2	input	Complementary reference clock input port 2 for PLL1 (CLKin2*), shared with the complementary OSCout output.
42	Vcc8_OSCin	power_in	Power supply for OSCin.
43	OSCin	input	Feedback to PLL1 and reference input to PLL2; AC-coupled (analog).
44	OSCin*	input	Complementary OSCin input; AC-coupled (analog) feedback to PLL1 and reference to PLL2.
45	Vcc9_CP2	power_in	Power supply for the PLL2 charge pump.
46	CPout2	output	Charge pump 2 output (analog) for PLL2.
47	Vcc10_PLL2	power_in	Power supply for PLL2.
48	Status_LD2	bidirectional	Programmable status pin (I/O, programmable).
49	SDCLKout9	output	Programmable SYSREF / device clock output 9 (true output).
50	SDCLKout9*	output	Complementary half of the SDCLKout9 differential output pair, as listed with 'Programmable SYSREF / Device clock 9'.
51	DCLKout8	output	Programmable device clock output 8 (true output).
52	DCLKout8*	output	Complementary half of the DCLKout8 differential output pair, as listed with 'Programmable Device clock output 8'.
53	Vcc11_CG3	power_in	Power supply for clock outputs 8, 9, 10 and 11.
54	DCLKout10	output	Programmable device clock output 10 (true output).
55	DCLKout10*	output	Complementary half of the DCLKout10 differential output pair, as listed with 'Programmable Device clock output 10'.
56	SDCLKout11	output	Programmable SYSREF / device clock output 11 (true output).
57	SDCLKout11*	output	Complementary half of the SDCLKout11 differential output pair, as listed with 'Programmable SYSREF / Device clock output 11'.
58	CLKin_SEL0	bidirectional	Programmable status pin (I/O) used for clock input selection.
59	CLKin_SEL1	bidirectional	Programmable status pin (I/O) used for clock input selection.
60	SDCLKout13	output	Programmable SYSREF / device clock output 13 (true output).
61	SDCLKout13*	output	Complementary half of the SDCLKout13 differential output pair, as listed with 'Programmable SYSREF / Device clock output 13'.
62	DCLKout12	output	Programmable device clock output 12 (true output).
63	DCLKout12*	output	Complementary half of the DCLKout12 differential output pair, as listed with 'Programmable Device clock output 12'.
64	Vcc12_CG0	power_in	Power supply for clock outputs 0, 1, 12 and 13.
65	DAP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WQFN-64-EP(9x9)
Category	RTC/Clock Chip
Pins	65

CAD (KiCad official)

Symbol: LMK04228NKDR
Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
3D model: WQFN-64-EP(9x9) (KiCad packages3D, STEP)
3D model files: lmk04228nkdr-etched.step / lmk04228nkdr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmk04228nkdr.step / lmk04228nkdr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (89 pp, sha256 3217c7afebcd700e, retrieved 2026-10-08, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF