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LMK01801BISQE

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Texas Instruments Clock Buffers, Drivers, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LMK01801BISQE

Texas Instruments · Clock Buffers, Drivers · VQFN-48-EP(7x7)

LMK01801BISQE from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LEuWire/CLKoutDIV_2 input MICROWIRE Latch Enable input in MICROWIRE mode; in pin control mode it selects the clock divider 2 setting (CMOS / 3-State input).
2 CLKout0 output Programmable clock output 0, selectable as LVDS or LVPECL, forming a differential pair with CLKout0*.
3 CLKout0* output Complementary programmable clock output 0 (LVDS or LVPECL), forming a differential pair with CLKout0.
4 CLKout1* output Complementary programmable clock output 1 (LVDS or LVPECL), forming a differential pair with CLKout1.
5 CLKout1 output Programmable clock output 1, selectable as LVDS or LVPECL, forming a differential pair with CLKout1*.
6 Vcc1_CLKout0_1_2_3 power_in Power supply for clock outputs 0, 1, 2 and 3; all Vcc pins must always be connected, with ferrite beads recommended on CLKout Vcc pins.
7 CLKout2 output Programmable clock output 2, selectable as LVDS or LVPECL, forming a differential pair with CLKout2*.
8 CLKout2* output Complementary programmable clock output 2 (LVDS or LVPECL), forming a differential pair with CLKout2.
9 CLKout3* output Complementary programmable clock output 3 (LVDS or LVPECL), forming a differential pair with CLKout3.
10 CLKout3 output Programmable clock output 3, selectable as LVDS or LVPECL, forming a differential pair with CLKout3*.
11 Test/CLKoutTYPE_0 bidirectional Reserved test pin; in pin control mode it selects the clock output type for CLKout0 to CLKout7 (CMOS / 3-State I/O).
12 SYNC0/CLKoutTYPE_1 input SYNC0 input for clock output synchronization of bank A; in pin control mode it selects the clock output type 1 (CMOS / 3-State input).
13 CLKin0 input Clock input 0 (bank A reference input), supporting clocking types including but not limited to LVDS, LVPECL and LVCMOS.
14 CLKin0* input Complementary clock input 0, used with CLKin0 for differential clocking types including but not limited to LVDS, LVPECL and LVCMOS.
15 Vcc2_CLKin0 power_in Power supply for clock input 0; all Vcc pins must always be connected.
16 CLKout4 output Programmable clock output 4, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout4*.
17 CLKout4* output Complementary programmable clock output 4 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout4.
18 CLKout5* output Complementary programmable clock output 5 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout5.
19 CLKout5 output Programmable clock output 5, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout5*.
20 Vcc3_CLKout4_5_6_7 power_in Power supply for clock outputs 4, 5, 6 and 7; all Vcc pins must always be connected.
21 CLKout6 output Programmable clock output 6, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout6*.
22 CLKout6* output Complementary programmable clock output 6 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout6.
23 CLKout7* output Complementary programmable clock output 7 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout7.
24 CLKout7 output Programmable clock output 7, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout7*.
25 Vcc4_Bias power_in Power supply for the Bias circuit; the Bias pin must be bypassed with a 1-µF capacitor to this pin for low-noise performance.
26 Bias passive Bias bypass pin, to be bypassed with a 1-µF capacitor connected to Vcc4_Bias (Pin 25) for low noise performance.
27 EN_PIN_CTRL input Selects MICROWIRE (SPI) or pin control mode (3-State input); floating selects SPI mode per the pin control mode tables.
28 CLKout8 output Programmable clock output 8, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout8*.
29 CLKout8* output Complementary programmable clock output 8 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout8.
30 CLKout9* output Complementary programmable clock output 9 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout9.
31 CLKout9 output Programmable clock output 9, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout9*.
32 Vcc5_CLKout8_9_10_11 power_in Power supply for clock outputs 8, 9, 10 and 11; all Vcc pins must always be connected.
33 CLKout10 output Programmable clock output 10, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout10*.
34 CLKout10* output Complementary programmable clock output 10 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout10.
35 CLKout11* output Complementary programmable clock output 11 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout11.
36 CLKout11 output Programmable clock output 11, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout11*.
37 Vcc6_CLKin1 power_in Power supply for clock input 1; all Vcc pins must always be connected.
38 CLKin1 input Clock input 1 (bank B reference input), supporting clocking types including but not limited to LVDS, LVPECL and LVCMOS.
39 CLKin1* input Complementary clock input 1, used with CLKin1 for differential clocking types including but not limited to LVDS, LVPECL and LVCMOS.
40 SYNC1/CLKoutTYPE_2 input SYNC pin for CLKin1 and bank B; in pin control mode it selects the clock output type 2 (CMOS / 3-State input).
41 Vcc7_CLKout12_13 power_in Power supply for clock outputs 12 and 13; all Vcc pins must always be connected.
42 CLKout12 output Programmable clock output 12, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout12*.
43 CLKout12* output Complementary programmable clock output 12 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout12.
44 CLKout13* output Complementary programmable clock output 13 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout13.
45 CLKout13 output Programmable clock output 13, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout13*.
46 Vcc8_DIG power_in Power supply for the digital core; all Vcc pins must always be connected.
47 DATAuWire/CLKoutDIV_0 input MICROWIRE DATA pin in MICROWIRE mode; in pin control mode it selects clock divider 0 (CMOS / 3-State input).
48 CLKuWire/CLKoutDIV_1 input MICROWIRE CLK pin in MICROWIRE mode; in pin control mode it selects clock divider 1 (CMOS / 3-State input).
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category RTC/Clock Chip
Pins 49

CAD (KiCad official)

  • Symbol: LMK01801BISQE
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: lmk01801bisqe-etched.step / lmk01801bisqe-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmk01801bisqe.step / lmk01801bisqe.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (59 pp, sha256 5a3a7e0e51658147, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF