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LMK01801BISQE
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Texas Instruments Clock Buffers, Drivers, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+86@@ -0,0 +1,86 @@+# LMK01801BISQE++**Texas Instruments** · Clock Buffers, Drivers · VQFN-48-EP(7x7)++LMK01801BISQE from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | LEuWire/CLKoutDIV_2 | input | MICROWIRE Latch Enable input in MICROWIRE mode; in pin control mode it selects the clock divider 2 setting (CMOS / 3-State input). |+| 2 | CLKout0 | output | Programmable clock output 0, selectable as LVDS or LVPECL, forming a differential pair with CLKout0*. |+| 3 | CLKout0* | output | Complementary programmable clock output 0 (LVDS or LVPECL), forming a differential pair with CLKout0. |+| 4 | CLKout1* | output | Complementary programmable clock output 1 (LVDS or LVPECL), forming a differential pair with CLKout1. |+| 5 | CLKout1 | output | Programmable clock output 1, selectable as LVDS or LVPECL, forming a differential pair with CLKout1*. |+| 6 | Vcc1_CLKout0_1_2_3 | power_in | Power supply for clock outputs 0, 1, 2 and 3; all Vcc pins must always be connected, with ferrite beads recommended on CLKout Vcc pins. |+| 7 | CLKout2 | output | Programmable clock output 2, selectable as LVDS or LVPECL, forming a differential pair with CLKout2*. |+| 8 | CLKout2* | output | Complementary programmable clock output 2 (LVDS or LVPECL), forming a differential pair with CLKout2. |+| 9 | CLKout3* | output | Complementary programmable clock output 3 (LVDS or LVPECL), forming a differential pair with CLKout3. |+| 10 | CLKout3 | output | Programmable clock output 3, selectable as LVDS or LVPECL, forming a differential pair with CLKout3*. |+| 11 | Test/CLKoutTYPE_0 | bidirectional | Reserved test pin; in pin control mode it selects the clock output type for CLKout0 to CLKout7 (CMOS / 3-State I/O). |+| 12 | SYNC0/CLKoutTYPE_1 | input | SYNC0 input for clock output synchronization of bank A; in pin control mode it selects the clock output type 1 (CMOS / 3-State input). |+| 13 | CLKin0 | input | Clock input 0 (bank A reference input), supporting clocking types including but not limited to LVDS, LVPECL and LVCMOS. |+| 14 | CLKin0* | input | Complementary clock input 0, used with CLKin0 for differential clocking types including but not limited to LVDS, LVPECL and LVCMOS. |+| 15 | Vcc2_CLKin0 | power_in | Power supply for clock input 0; all Vcc pins must always be connected. |+| 16 | CLKout4 | output | Programmable clock output 4, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout4*. |+| 17 | CLKout4* | output | Complementary programmable clock output 4 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout4. |+| 18 | CLKout5* | output | Complementary programmable clock output 5 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout5. |+| 19 | CLKout5 | output | Programmable clock output 5, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout5*. |+| 20 | Vcc3_CLKout4_5_6_7 | power_in | Power supply for clock outputs 4, 5, 6 and 7; all Vcc pins must always be connected. |+| 21 | CLKout6 | output | Programmable clock output 6, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout6*. |+| 22 | CLKout6* | output | Complementary programmable clock output 6 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout6. |+| 23 | CLKout7* | output | Complementary programmable clock output 7 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout7. |+| 24 | CLKout7 | output | Programmable clock output 7, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout7*. |+| 25 | Vcc4_Bias | power_in | Power supply for the Bias circuit; the Bias pin must be bypassed with a 1-µF capacitor to this pin for low-noise performance. |+| 26 | Bias | passive | Bias bypass pin, to be bypassed with a 1-µF capacitor connected to Vcc4_Bias (Pin 25) for low noise performance. |+| 27 | EN_PIN_CTRL | input | Selects MICROWIRE (SPI) or pin control mode (3-State input); floating selects SPI mode per the pin control mode tables. |+| 28 | CLKout8 | output | Programmable clock output 8, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout8*. |+| 29 | CLKout8* | output | Complementary programmable clock output 8 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout8. |+| 30 | CLKout9* | output | Complementary programmable clock output 9 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout9. |+| 31 | CLKout9 | output | Programmable clock output 9, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout9*. |+| 32 | Vcc5_CLKout8_9_10_11 | power_in | Power supply for clock outputs 8, 9, 10 and 11; all Vcc pins must always be connected. |+| 33 | CLKout10 | output | Programmable clock output 10, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout10*. |+| 34 | CLKout10* | output | Complementary programmable clock output 10 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout10. |+| 35 | CLKout11* | output | Complementary programmable clock output 11 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout11. |+| 36 | CLKout11 | output | Programmable clock output 11, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout11*. |+| 37 | Vcc6_CLKin1 | power_in | Power supply for clock input 1; all Vcc pins must always be connected. |+| 38 | CLKin1 | input | Clock input 1 (bank B reference input), supporting clocking types including but not limited to LVDS, LVPECL and LVCMOS. |+| 39 | CLKin1* | input | Complementary clock input 1, used with CLKin1 for differential clocking types including but not limited to LVDS, LVPECL and LVCMOS. |+| 40 | SYNC1/CLKoutTYPE_2 | input | SYNC pin for CLKin1 and bank B; in pin control mode it selects the clock output type 2 (CMOS / 3-State input). |+| 41 | Vcc7_CLKout12_13 | power_in | Power supply for clock outputs 12 and 13; all Vcc pins must always be connected. |+| 42 | CLKout12 | output | Programmable clock output 12, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout12*. |+| 43 | CLKout12* | output | Complementary programmable clock output 12 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout12. |+| 44 | CLKout13* | output | Complementary programmable clock output 13 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout13. |+| 45 | CLKout13 | output | Programmable clock output 13, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout13*. |+| 46 | Vcc8_DIG | power_in | Power supply for the digital core; all Vcc pins must always be connected. |+| 47 | DATAuWire/CLKoutDIV_0 | input | MICROWIRE DATA pin in MICROWIRE mode; in pin control mode it selects clock divider 0 (CMOS / 3-State input). |+| 48 | CLKuWire/CLKoutDIV_1 | input | MICROWIRE CLK pin in MICROWIRE mode; in pin control mode it selects clock divider 1 (CMOS / 3-State input). |+| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-48-EP(7x7) |+| Category | RTC/Clock Chip |+| Pins | 49 |++## CAD (KiCad official)++- Symbol: `LMK01801BISQE`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`+- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)+- 3D model files: `lmk01801bisqe-etched.step` / `lmk01801bisqe-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lmk01801bisqe.step` / `lmk01801bisqe.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lmk01801) (59 pp, sha256 `5a3a7e0e51658147`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/lmk01801bisqe-datasheet.pdf)
page.jsonadded+445@@ -0,0 +1,445 @@+{+ "slug": "lmk01801bisqe",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Clock Buffers, Drivers, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "rtc-clock chip",+ "lmk01801bisqe",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "lmk01801bisqe.kicad_sym",+ "lmk01801bisqe.kicad_mod",+ "lmk01801bisqe.glb",+ "lmk01801bisqe.step",+ "lmk01801bisqe.lbr",+ "docs/hero.png",+ "docs/lmk01801bisqe-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "lmk01801bisqe-hero.glb",+ "lmk01801bisqe-hero.overlay.json"+ ],+ "component": {+ "mpn": "LMK01801BISQE",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-48-EP(7x7)",+ "pin_count": 49,+ "category": "RTC/Clock Chip",+ "subcategory": "Clock Buffers, Drivers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/lmk01801",+ "parts": {+ "symbol": "lmk01801bisqe.kicad_sym",+ "footprint": "lmk01801bisqe.kicad_mod",+ "model_3d": "lmk01801bisqe-hero.glb",+ "model_3d_plain": "lmk01801bisqe.glb",+ "model_3d_step": "lmk01801bisqe-etched.step",+ "model_3d_step_plain": "lmk01801bisqe.step",+ "lbr": "lmk01801bisqe.lbr"+ },+ "distributor_links": {+ "lcsc": "C2673010"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T18:44:10Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "no match"+ },+ "mouser": {+ "pn": null,+ "status": "no match"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "LEuWire/CLKoutDIV_2",+ "type": "input",+ "description": "MICROWIRE Latch Enable input in MICROWIRE mode; in pin control mode it selects the clock divider 2 setting (CMOS / 3-State input)."+ },+ {+ "number": "2",+ "name": "CLKout0",+ "type": "output",+ "description": "Programmable clock output 0, selectable as LVDS or LVPECL, forming a differential pair with CLKout0*."+ },+ {+ "number": "3",+ "name": "CLKout0*",+ "type": "output",+ "description": "Complementary programmable clock output 0 (LVDS or LVPECL), forming a differential pair with CLKout0."+ },+ {+ "number": "4",+ "name": "CLKout1*",+ "type": "output",+ "description": "Complementary programmable clock output 1 (LVDS or LVPECL), forming a differential pair with CLKout1."+ },+ {+ "number": "5",+ "name": "CLKout1",+ "type": "output",+ "description": "Programmable clock output 1, selectable as LVDS or LVPECL, forming a differential pair with CLKout1*."+ },+ {+ "number": "6",+ "name": "Vcc1_CLKout0_1_2_3",+ "type": "power_in",+ "description": "Power supply for clock outputs 0, 1, 2 and 3; all Vcc pins must always be connected, with ferrite beads recommended on CLKout Vcc pins."+ },+ {+ "number": "7",+ "name": "CLKout2",+ "type": "output",+ "description": "Programmable clock output 2, selectable as LVDS or LVPECL, forming a differential pair with CLKout2*."+ },+ {+ "number": "8",+ "name": "CLKout2*",+ "type": "output",+ "description": "Complementary programmable clock output 2 (LVDS or LVPECL), forming a differential pair with CLKout2."+ },+ {+ "number": "9",+ "name": "CLKout3*",+ "type": "output",+ "description": "Complementary programmable clock output 3 (LVDS or LVPECL), forming a differential pair with CLKout3."+ },+ {+ "number": "10",+ "name": "CLKout3",+ "type": "output",+ "description": "Programmable clock output 3, selectable as LVDS or LVPECL, forming a differential pair with CLKout3*."+ },+ {+ "number": "11",+ "name": "Test/CLKoutTYPE_0",+ "type": "bidirectional",+ "description": "Reserved test pin; in pin control mode it selects the clock output type for CLKout0 to CLKout7 (CMOS / 3-State I/O)."+ },+ {+ "number": "12",+ "name": "SYNC0/CLKoutTYPE_1",+ "type": "input",+ "description": "SYNC0 input for clock output synchronization of bank A; in pin control mode it selects the clock output type 1 (CMOS / 3-State input)."+ },+ {+ "number": "13",+ "name": "CLKin0",+ "type": "input",+ "description": "Clock input 0 (bank A reference input), supporting clocking types including but not limited to LVDS, LVPECL and LVCMOS."+ },+ {+ "number": "14",+ "name": "CLKin0*",+ "type": "input",+ "description": "Complementary clock input 0, used with CLKin0 for differential clocking types including but not limited to LVDS, LVPECL and LVCMOS."+ },+ {+ "number": "15",+ "name": "Vcc2_CLKin0",+ "type": "power_in",+ "description": "Power supply for clock input 0; all Vcc pins must always be connected."+ },+ {+ "number": "16",+ "name": "CLKout4",+ "type": "output",+ "description": "Programmable clock output 4, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout4*."+ },+ {+ "number": "17",+ "name": "CLKout4*",+ "type": "output",+ "description": "Complementary programmable clock output 4 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout4."+ },+ {+ "number": "18",+ "name": "CLKout5*",+ "type": "output",+ "description": "Complementary programmable clock output 5 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout5."+ },+ {+ "number": "19",+ "name": "CLKout5",+ "type": "output",+ "description": "Programmable clock output 5, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout5*."+ },+ {+ "number": "20",+ "name": "Vcc3_CLKout4_5_6_7",+ "type": "power_in",+ "description": "Power supply for clock outputs 4, 5, 6 and 7; all Vcc pins must always be connected."+ },+ {+ "number": "21",+ "name": "CLKout6",+ "type": "output",+ "description": "Programmable clock output 6, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout6*."+ },+ {+ "number": "22",+ "name": "CLKout6*",+ "type": "output",+ "description": "Complementary programmable clock output 6 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout6."+ },+ {+ "number": "23",+ "name": "CLKout7*",+ "type": "output",+ "description": "Complementary programmable clock output 7 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout7."+ },+ {+ "number": "24",+ "name": "CLKout7",+ "type": "output",+ "description": "Programmable clock output 7, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout7*."+ },+ {+ "number": "25",+ "name": "Vcc4_Bias",+ "type": "power_in",+ "description": "Power supply for the Bias circuit; the Bias pin must be bypassed with a 1-µF capacitor to this pin for low-noise performance."+ },+ {+ "number": "26",+ "name": "Bias",+ "type": "passive",+ "description": "Bias bypass pin, to be bypassed with a 1-µF capacitor connected to Vcc4_Bias (Pin 25) for low noise performance."+ },+ {+ "number": "27",+ "name": "EN_PIN_CTRL",+ "type": "input",+ "description": "Selects MICROWIRE (SPI) or pin control mode (3-State input); floating selects SPI mode per the pin control mode tables."+ },+ {+ "number": "28",+ "name": "CLKout8",+ "type": "output",+ "description": "Programmable clock output 8, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout8*."+ },+ {+ "number": "29",+ "name": "CLKout8*",+ "type": "output",+ "description": "Complementary programmable clock output 8 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout8."+ },+ {+ "number": "30",+ "name": "CLKout9*",+ "type": "output",+ "description": "Complementary programmable clock output 9 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout9."+ },+ {+ "number": "31",+ "name": "CLKout9",+ "type": "output",+ "description": "Programmable clock output 9, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout9*."+ },+ {+ "number": "32",+ "name": "Vcc5_CLKout8_9_10_11",+ "type": "power_in",+ "description": "Power supply for clock outputs 8, 9, 10 and 11; all Vcc pins must always be connected."+ },+ {+ "number": "33",+ "name": "CLKout10",+ "type": "output",+ "description": "Programmable clock output 10, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout10*."+ },+ {+ "number": "34",+ "name": "CLKout10*",+ "type": "output",+ "description": "Complementary programmable clock output 10 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout10."+ },+ {+ "number": "35",+ "name": "CLKout11*",+ "type": "output",+ "description": "Complementary programmable clock output 11 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout11."+ },+ {+ "number": "36",+ "name": "CLKout11",+ "type": "output",+ "description": "Programmable clock output 11, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout11*."+ },+ {+ "number": "37",+ "name": "Vcc6_CLKin1",+ "type": "power_in",+ "description": "Power supply for clock input 1; all Vcc pins must always be connected."+ },+ {+ "number": "38",+ "name": "CLKin1",+ "type": "input",+ "description": "Clock input 1 (bank B reference input), supporting clocking types including but not limited to LVDS, LVPECL and LVCMOS."+ },+ {+ "number": "39",+ "name": "CLKin1*",+ "type": "input",+ "description": "Complementary clock input 1, used with CLKin1 for differential clocking types including but not limited to LVDS, LVPECL and LVCMOS."+ },+ {+ "number": "40",+ "name": "SYNC1/CLKoutTYPE_2",+ "type": "input",+ "description": "SYNC pin for CLKin1 and bank B; in pin control mode it selects the clock output type 2 (CMOS / 3-State input)."+ },+ {+ "number": "41",+ "name": "Vcc7_CLKout12_13",+ "type": "power_in",+ "description": "Power supply for clock outputs 12 and 13; all Vcc pins must always be connected."+ },+ {+ "number": "42",+ "name": "CLKout12",+ "type": "output",+ "description": "Programmable clock output 12, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout12*."+ },+ {+ "number": "43",+ "name": "CLKout12*",+ "type": "output",+ "description": "Complementary programmable clock output 12 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout12."+ },+ {+ "number": "44",+ "name": "CLKout13*",+ "type": "output",+ "description": "Complementary programmable clock output 13 (LVDS, LVPECL or LVCMOS), forming a differential pair with CLKout13."+ },+ {+ "number": "45",+ "name": "CLKout13",+ "type": "output",+ "description": "Programmable clock output 13, selectable as LVDS, LVPECL or LVCMOS, forming a differential pair with CLKout13*."+ },+ {+ "number": "46",+ "name": "Vcc8_DIG",+ "type": "power_in",+ "description": "Power supply for the digital core; all Vcc pins must always be connected."+ },+ {+ "number": "47",+ "name": "DATAuWire/CLKoutDIV_0",+ "type": "input",+ "description": "MICROWIRE DATA pin in MICROWIRE mode; in pin control mode it selects clock divider 0 (CMOS / 3-State input)."+ },+ {+ "number": "48",+ "name": "CLKuWire/CLKoutDIV_1",+ "type": "input",+ "description": "MICROWIRE CLK pin in MICROWIRE mode; in pin control mode it selects clock divider 1 (CMOS / 3-State input)."+ },+ {+ "number": "49",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Package naming differs from the hint: the datasheet calls this package VQFN (48) 7.00 mm x 7.00 mm, ; Pin 11, 12, 27, 40, 47 and 48 have dual functions (MICROWIRE / SYNC / pin control mode). Which funct; Pin types for the CLKin and Bias pins are not given as KiCad classes in the datasheet. CLKin0/CLKin1",+ "exposed pad 49 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 13,+ "cost_usd": 0.1147,+ "at": "2026-10-08T18:43:20"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/lmk01801",+ "pages": 59,+ "sha256": "5a3a7e0e51658147",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 49,+ "described": 49,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "lmk01801bisqe.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "lmk01801bisqe-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "491e18aae5240617603dbb0feedcffcc85d2b8158fe6f736fd960802040abbdb",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}