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LMK00804BQWRGTTQ1

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Texas Instruments Clock Buffers, Drivers, VQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LMK00804BQWRGTTQ1

Texas Instruments · Clock Buffers, Drivers · VQFN-16-EP(3x3)

LMK00804BQWRGTTQ1 from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Power supply ground.
2 NC unconnected No-connect pin, typically left floating and not to be connected to GND.
3 VDD power_in Power supply terminal, typically 3.3 V (recommended 3.135 V to 3.465 V), with a typical 0.1 µF decoupling capacitor to GND.
4 CLK_EN input Synchronous clock enable input that must be held low until a valid reference clock is provided; low forces outputs to logic low and high enables the LVCMOS/LVTTL outputs, with an internal pullup (typically 1 kΩ to VDD external) and left floating when unused.
5 CLK_P input Noninverting differential clock input with internal 51 kΩ (typ) pulldown to GND, which can also accept a single-ended clock; leave floating when unused.
6 CLK_N input Inverting differential clock input with internal 51 kΩ (typ) pullup to VDD and 51 kΩ (typ) pulldown to GND, internally biased to VDD/2 when floating.
7 CLK_SEL input Clock select input, typically pulled up to VDD with an external 1 kΩ; low selects LVCMOS_CLK (pin 8) and high selects CLK_P/CLK_N (pins 5, 6).
8 LVCMOS_CLK input Single-ended clock input with internal 51 kΩ (typ) pulldown to GND that accepts LVCMOS/LVTTL levels; leave floating when unused.
9 GND power_in Power supply ground.
10 Q3 output Single-ended clock output with LVCMOS/LVTTL levels at 7 Ω output impedance, typically driven into a 43 Ω series termination; leave unconnected when unused.
11 VDDO power_in Output supply terminal, typically 3.3 V, 2.5 V, 1.8 V or 1.5 V, with a typical 0.1 µF decoupling capacitor to GND.
12 Q2 output Single-ended clock output with LVCMOS/LVTTL levels at 7 Ω output impedance, typically driven into a 43 Ω series termination; leave unconnected when unused.
13 GND power_in Power supply ground.
14 Q1 output Single-ended clock output with LVCMOS/LVTTL levels at 7 Ω output impedance, typically driven into a 43 Ω series termination; leave unconnected when unused.
15 VDDO power_in Output supply terminal, typically 3.3 V, 2.5 V, 1.8 V or 1.5 V, with a typical 0.1 µF decoupling capacitor to GND.
16 Q0 output Single-ended clock output with LVCMOS/LVTTL levels at 7 Ω output impedance, typically driven into a 43 Ω series termination; leave unconnected when unused.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-16-EP(3x3)
Category RTC/Clock Chip
Pins 17

CAD (KiCad official)

  • Symbol: LMK00804BQWRGTTQ1
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: lmk00804bqwrgttq1-etched.step / lmk00804bqwrgttq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmk00804bqwrgttq1.step / lmk00804bqwrgttq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (29 pp, sha256 b58ecb79387c6fb9, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF