component
LMK00725PWR
Public Made by Adomby adom
Texas Instruments Clock Buffers, Drivers, Distributors, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"schema_version": 1,
"type": "component",
"slug": "lmk00725pwr",
"title": "LMK00725PWR",
"brief": "Texas Instruments Clock Buffers, Drivers, Distributors, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
"tags": [
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"clock-timing",
"lmk00725pwr",
"factory-2.0.0",
"extractor-text"
],
"component": {
"mpn": "LMK00725PWR",
"manufacturer": "Texas Instruments",
"package": "TSSOP-20",
"pin_count": 20,
"category": "Clock/Timing",
"subcategory": "Clock Buffers, Drivers, Distributors",
"datasheet": "https://www.ti.com/lit/ds/symlink/lmk00725.pdf",
"parts": {
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"footprint": "lmk00725pwr.kicad_mod",
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"lbr": "lmk00725pwr.lbr"
},
"distributor_links": {
"lcsc": "C2869763",
"digikey": "296-LMK00725PWRTR-ND",
"mouser": "595-LMK00725PWR"
},
"distributor_check": {
"checked_at": "2026-10-07T22:47:42Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "296-LMK00725PWRTR-ND",
"status": "found",
"lifecycle": "Active"
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}
},
"pins": [
{
"number": "1",
"name": "Q0",
"type": "output",
"description": "Non-inverting LVPECL output of differential output pair 0; forced LOW when CLK_EN is 0 and follows the selected clock input when CLK_EN is 1."
},
{
"number": "2",
"name": "nQ0",
"type": "output",
"description": "Inverting LVPECL output of differential output pair 0; forced HIGH when CLK_EN is 0 and the complement of Q0 when enabled."
},
{
"number": "3",
"name": "Q1",
"type": "output",
"description": "Non-inverting LVPECL output of differential output pair 1; forced LOW when CLK_EN is 0 and follows the selected clock input when CLK_EN is 1."
},
{
"number": "4",
"name": "nQ1",
"type": "output",
"description": "Inverting LVPECL output of differential output pair 1; forced HIGH when CLK_EN is 0 and the complement of Q1 when enabled."
},
{
"number": "5",
"name": "Q2",
"type": "output",
"description": "Non-inverting LVPECL output of differential output pair 2; forced LOW when CLK_EN is 0 and follows the selected clock input when CLK_EN is 1."
},
{
"number": "6",
"name": "nQ2",
"type": "output",
"description": "Inverting LVPECL output of differential output pair 2; forced HIGH when CLK_EN is 0 and the complement of Q2 when enabled."
},
{
"number": "7",
"name": "Q3",
"type": "output",
"description": "Non-inverting LVPECL output of differential output pair 3; forced LOW when CLK_EN is 0 and follows the selected clock input when CLK_EN is 1."
},
{
"number": "8",
"name": "nQ3",
"type": "output",
"description": "Inverting LVPECL output of differential output pair 3; forced HIGH when CLK_EN is 0 and the complement of Q3 when enabled."
},
{
"number": "9",
"name": "Q4",
"type": "output",
"description": "Non-inverting LVPECL output of differential output pair 4; forced LOW when CLK_EN is 0 and follows the selected clock input when CLK_EN is 1. Unused outputs may be left floating."
},
{
"number": "10",
"name": "nQ4",
"type": "output",
"description": "Inverting LVPECL output of differential output pair 4; forced HIGH when CLK_EN is 0 and the complement of Q4 when enabled. Unused outputs may be left floating."
},
{
"number": "11",
"name": "VCC",
"type": "power_in",
"description": "Positive supply pin; 3.3 V nominal with a 3.135 V to 3.465 V recommended range (VEE = GND)."
},
{
"number": "12",
"name": "CLK_SEL",
"type": "input",
"description": "LVCMOS/TTL-compatible clock select input: 0 selects CLK0/nCLK0 and 1 selects CLK1/nCLK1; internal 51 kΩ pulldown, floating defaults to channel 0."
},
{
"number": "13",
"name": "CLK0",
"type": "input",
"description": "Non-inverting differential clock input 0 with internal 51 kΩ pulldown; accepts LVPECL, LVDS, HCSL, SSTL, LVHSTL or single-ended signals."
},
{
"number": "14",
"name": "nCLK0",
"type": "input",
"description": "Inverting differential clock input 0 with internal 51 kΩ pullup; biased per the input DC configuration when used single-ended."
},
{
"number": "15",
"name": "VEE",
"type": "power_in",
"description": "Negative supply pin, connected to ground (VEE = GND) per the recommended operating conditions."
},
{
"number": "16",
"name": "CLK1",
"type": "input",
"description": "Non-inverting differential clock input 1 with internal 51 kΩ pulldown; accepts LVPECL, LVDS, HCSL, SSTL, LVHSTL or single-ended signals."
},
{
"number": "17",
"name": "nCLK1",
"type": "input",
"description": "Inverting differential clock input 1 with internal 51 kΩ pullup; biased per the input DC configuration when used single-ended."
},
{
"number": "18",
"name": "VCC",
"type": "power_in",
"description": "Positive supply pin; 3.3 V nominal with a 3.135 V to 3.465 V recommended range (VEE = GND)."
},
{
"number": "19",
"name": "CLK_EN",
"type": "input",
"description": "Synchronous LVCMOS/TTL clock enable input: 0 forces Qx low and nQx high, 1 enables outputs to follow the clock input; internal 51 kΩ pullup."
},
{
"number": "20",
"name": "VCC",
"type": "power_in",
"description": "Positive supply pin; 3.3 V nominal with a 3.135 V to 3.465 V recommended range (VEE = GND)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Pinout taken from the Table 1 pin description and Figure 2 pinout diagram on page 2 for the TSSOP-20; Pin types mapped to KiCad classes: LVPECL outputs as output, CLK/nCLK/control pins as input, and VCC"
],
"pages_sent": 25,
"cost_usd": 0.1042,
"at": "2026-10-07T22:47:22"
},
"datasheet": {
"url": "https://www.ti.com/lit/ds/symlink/lmk00725.pdf",
"pages": 25,
"sha256": "c4dd7bad8054600a",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 20,
"described": 20,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
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"footprint": "viewers/footprint.html"
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"seat": "z = 0",
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6.5,
1.2
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"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "97339947f3a7196470ec2f1d9f9b92bb2fc2ab66ad53be0cf105192585ef3c9a",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
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]
},
"metadata": {
"specs": {
"Manufacturer": "Texas Instruments",
"Package": "TSSOP-20",
"Category": "Clock/Timing",
"Pins": "20"
}
},
"variants": [],
"sections": [
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"discovery_triggers": [
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"discovery_pitch": "LMK00725PWR (Texas Instruments) component page: datasheet pinout, KiCad symbol, footprint and 3D.",
"author": {
"name": "Ray",
"email": "[email protected]"
},
"dependencies": {},
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"files": [
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