component

LMK00725PWR

Public Made by Adom

by adom

Texas Instruments Clock Buffers, Drivers, Distributors, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock-timinglmk00725pwrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1d ago
viewers lmk00725pwr: viewers · Ray 1d ago
lmk00725pwr-etched.glb lmk00725pwr: factory component page (tier=mfr) · Ray 1d ago
lmk00725pwr-etched.step lmk00725pwr: factory component page (tier=mfr) · Ray 1d ago
lmk00725pwr-hero.glb lmk00725pwr: hero GLB from the etched model (keeps the MPN mark) · Ray 21h ago
lmk00725pwr-hero.overlay.json Publish 0.1.0 · Ray 1d ago
lmk00725pwr.glb Publish 0.1.0 · Ray 1d ago
lmk00725pwr.kicad_mod Publish 0.1.0 · Ray 1d ago
lmk00725pwr.kicad_sym Publish 0.1.0 · Ray 1d ago
lmk00725pwr.lbr Publish 0.1.0 · Ray 1d ago
lmk00725pwr.step Publish 0.1.0 · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Initial commit: component/lmk00725pwr · Ray 1d ago

LMK00725PWR

Texas Instruments · Clock Buffers, Drivers, Distributors · TSSOP-20

LMK00725PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q0 output Non-inverting LVPECL output of differential output pair 0; forced LOW when CLK_EN is 0 and follows the selected clock input when CLK_EN is 1.
2 nQ0 output Inverting LVPECL output of differential output pair 0; forced HIGH when CLK_EN is 0 and the complement of Q0 when enabled.
3 Q1 output Non-inverting LVPECL output of differential output pair 1; forced LOW when CLK_EN is 0 and follows the selected clock input when CLK_EN is 1.
4 nQ1 output Inverting LVPECL output of differential output pair 1; forced HIGH when CLK_EN is 0 and the complement of Q1 when enabled.
5 Q2 output Non-inverting LVPECL output of differential output pair 2; forced LOW when CLK_EN is 0 and follows the selected clock input when CLK_EN is 1.
6 nQ2 output Inverting LVPECL output of differential output pair 2; forced HIGH when CLK_EN is 0 and the complement of Q2 when enabled.
7 Q3 output Non-inverting LVPECL output of differential output pair 3; forced LOW when CLK_EN is 0 and follows the selected clock input when CLK_EN is 1.
8 nQ3 output Inverting LVPECL output of differential output pair 3; forced HIGH when CLK_EN is 0 and the complement of Q3 when enabled.
9 Q4 output Non-inverting LVPECL output of differential output pair 4; forced LOW when CLK_EN is 0 and follows the selected clock input when CLK_EN is 1. Unused outputs may be left floating.
10 nQ4 output Inverting LVPECL output of differential output pair 4; forced HIGH when CLK_EN is 0 and the complement of Q4 when enabled. Unused outputs may be left floating.
11 VCC power_in Positive supply pin; 3.3 V nominal with a 3.135 V to 3.465 V recommended range (VEE = GND).
12 CLK_SEL input LVCMOS/TTL-compatible clock select input: 0 selects CLK0/nCLK0 and 1 selects CLK1/nCLK1; internal 51 kΩ pulldown, floating defaults to channel 0.
13 CLK0 input Non-inverting differential clock input 0 with internal 51 kΩ pulldown; accepts LVPECL, LVDS, HCSL, SSTL, LVHSTL or single-ended signals.
14 nCLK0 input Inverting differential clock input 0 with internal 51 kΩ pullup; biased per the input DC configuration when used single-ended.
15 VEE power_in Negative supply pin, connected to ground (VEE = GND) per the recommended operating conditions.
16 CLK1 input Non-inverting differential clock input 1 with internal 51 kΩ pulldown; accepts LVPECL, LVDS, HCSL, SSTL, LVHSTL or single-ended signals.
17 nCLK1 input Inverting differential clock input 1 with internal 51 kΩ pullup; biased per the input DC configuration when used single-ended.
18 VCC power_in Positive supply pin; 3.3 V nominal with a 3.135 V to 3.465 V recommended range (VEE = GND).
19 CLK_EN input Synchronous LVCMOS/TTL clock enable input: 0 forces Qx low and nQx high, 1 enables outputs to follow the clock input; internal 51 kΩ pullup.
20 VCC power_in Positive supply pin; 3.3 V nominal with a 3.135 V to 3.465 V recommended range (VEE = GND).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Clock/Timing
Pins 20

CAD (KiCad official)

  • Symbol: LMK00725PWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: lmk00725pwr-etched.step / lmk00725pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmk00725pwr.step / lmk00725pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 c4dd7bad8054600a, retrieved 2026-10-07, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF