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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

LMK00301SQX

Texas Instruments · Clock Buffers, Drivers · WQFN-48-EP(7x7)

LMK00301SQX from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CLKoutA0	output	Differential clock output A0 (LVPECL, LVDS, HCSL, or high-Z), with the type set by the CLKoutA_TYPE pins.
2	CLKoutA0*	output	Complementary differential clock output A0* (LVPECL, LVDS, HCSL, or high-Z), with the type set by the CLKoutA_TYPE pins.
3	CLKoutA1	output	Differential clock output A1 (LVPECL, LVDS, HCSL, or high-Z), with the type set by the CLKoutA_TYPE pins.
4	CLKoutA1*	output	Complementary differential clock output A1* (LVPECL, LVDS, HCSL, or high-Z), with the type set by the CLKoutA_TYPE pins.
5	VCCOA	power_in	Output buffer supply for bank A, operating at 3.3 V or 2.5 V (±5%); VCCOA pins are internally connected and must not exceed VCC.
6	CLKoutA2	output	Differential clock output A2 (LVPECL, LVDS, HCSL, or high-Z), with the type set by the CLKoutA_TYPE pins.
7	CLKoutA2*	output	Complementary differential clock output A2* (LVPECL, LVDS, HCSL, or high-Z), with the type set by the CLKoutA_TYPE pins.
8	VCCOA	power_in	Output buffer supply for bank A, operating at 3.3 V or 2.5 V (±5%); VCCOA pins are internally connected and must not exceed VCC.
9	CLKoutA3	output	Differential clock output A3 (LVPECL, LVDS, HCSL, or high-Z), with the type set by the CLKoutA_TYPE pins.
10	CLKoutA3*	output	Complementary differential clock output A3* (LVPECL, LVDS, HCSL, or high-Z), with the type set by the CLKoutA_TYPE pins.
11	CLKoutA4	output	Differential clock output A4 (LVPECL, LVDS, HCSL, or high-Z), with the type set by the CLKoutA_TYPE pins.
12	CLKoutA4*	output	Complementary differential clock output A4* (LVPECL, LVDS, HCSL, or high-Z), with the type set by the CLKoutA_TYPE pins.
13	GND	power_in	Ground pin.
14	CLKoutA_TYPE0	input	CMOS control input with internal pull-down that selects the bank A output buffer type together with CLKoutA_TYPE1.
15	VCC	power_in	Core and input buffer block supply, operating at 3.3 V; bypass with a 0.1 µF low-ESR capacitor placed close to each VCC pin.
16	OSCin	input	Crystal input, which can also be driven by an XO, TCXO, or other external single-ended clock (up to 250 MHz).
17	OSCout	output	Crystal output; leave floating when OSCin is driven by a single-ended clock.
18	GND	power_in	Ground pin.
19	CLKin_SEL0	input	CMOS clock input select control with internal pull-down that selects CLKin0, CLKin1, or OSCin together with CLKin_SEL1.
20	CLKin0	input	Universal clock input 0, accepting differential or single-ended signals and operating up to 3.1 GHz.
21	CLKin0*	input	Complementary universal clock input 0*, used with CLKin0 for differential operation or biased externally for single-ended operation.
22	CLKin_SEL1	input	CMOS clock input select control with internal pull-down that selects CLKin0, CLKin1, or OSCin together with CLKin_SEL0.
23	CLKoutB_TYPE0	input	CMOS control input with internal pull-down that selects the bank B output buffer type together with CLKoutB_TYPE1.
24	GND	power_in	Ground pin.
25	CLKoutB4*	output	Complementary differential clock output B4* (LVPECL, LVDS, HCSL, or high-Z), with the type set by the CLKoutB_TYPE pins.
26	CLKoutB4	output	Differential clock output B4 (LVPECL, LVDS, HCSL, or high-Z), with the type set by the CLKoutB_TYPE pins.
27	CLKoutB3*	output	Complementary differential clock output B3* (LVPECL, LVDS, HCSL, or high-Z), with the type set by the CLKoutB_TYPE pins.
28	CLKoutB3	output	Differential clock output B3 (LVPECL, LVDS, HCSL, or high-Z), with the type set by the CLKoutB_TYPE pins.
29	VCCOB	power_in	Output buffer supply for bank B, operating at 3.3 V or 2.5 V (±5%); VCCOB pins are internally connected and must not exceed VCC.
30	CLKoutB2*	output	Complementary differential clock output B2* (LVPECL, LVDS, HCSL, or high-Z), with the type set by the CLKoutB_TYPE pins.
31	CLKoutB2	output	Differential clock output B2 (LVPECL, LVDS, HCSL, or high-Z), with the type set by the CLKoutB_TYPE pins.
32	VCCOB	power_in	Output buffer supply for bank B, operating at 3.3 V or 2.5 V (±5%); VCCOB pins are internally connected and must not exceed VCC.
33	CLKoutB1*	output	Complementary differential clock output B1* (LVPECL, LVDS, HCSL, or high-Z), with the type set by the CLKoutB_TYPE pins.
34	CLKoutB1	output	Differential clock output B1 (LVPECL, LVDS, HCSL, or high-Z), with the type set by the CLKoutB_TYPE pins.
35	CLKoutB0*	output	Complementary differential clock output B0* (LVPECL, LVDS, HCSL, or high-Z), with the type set by the CLKoutB_TYPE pins.
36	CLKoutB0	output	Differential clock output B0 (LVPECL, LVDS, HCSL, or high-Z), with the type set by the CLKoutB_TYPE pins.
37	GND	power_in	Ground pin.
38	NC	unconnected	Internally not connected; may be left floating, grounded, or tied to any potential within the absolute maximum supply voltage range.
39	CLKoutB_TYPE1	input	CMOS control input with internal pull-down that selects the bank B output buffer type together with CLKoutB_TYPE0.
40	CLKin1	input	Universal clock input 1, accepting differential or single-ended signals and operating up to 3.1 GHz.
41	CLKin1*	input	Complementary universal clock input 1*, used with CLKin1 for differential operation or biased externally for single-ended operation.
42	VCC	power_in	Core and input buffer block supply, operating at 3.3 V; bypass with a 0.1 µF low-ESR capacitor placed close to each VCC pin.
43	GND	power_in	Ground pin.
44	REFout	output	LVCMOS reference output referenced to VCCOC, enabled by pulling REFout_EN high and disabled (high-Z) when REFout_EN is low.
45	VCCOC	power_in	Output buffer supply for the REFout output, operating at 3.3 V or 2.5 V (±5%).
46	REFout_EN	input	CMOS REFout enable input with internal pull-down, synchronized internally to the selected input clock to avoid glitches.
47	CLKoutA_TYPE1	input	CMOS control input with internal pull-down that selects the bank A output buffer type together with CLKoutA_TYPE0.
48	GND	power_in	Ground pin.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WQFN-48-EP(7x7)
Category	RTC/Clock Chip
Pins	49

CAD (KiCad official)

Symbol: LMK00301SQX
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)
3D model files: lmk00301sqx-etched.step / lmk00301sqx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmk00301sqx.step / lmk00301sqx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (45 pp, sha256 6962bb9414ac1c54, retrieved 2026-10-07, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF