component
LM74910QRGERQ1
Public Made by Adomby adom
Texas Instruments Power Distribution Switches, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownLM74910QRGERQ1
Texas Instruments · Power Distribution Switches · VQFN-24-EP(4x4)
LM74910QRGERQ1 from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DGATE | output | Diode controller gate-drive output that connects to the gate of the external ideal-diode MOSFET. |
| 2 | A | input | Anode of the ideal diode; connects to the source of the external MOSFET (Q1) and is monitored for the AC-DC forward regulation and fast reverse-voltage comparator. |
| 3 | SW | input | Voltage-sense disconnect switch terminal internally connected to VSNS; used as the top connection for the battery-detect or OV resistor ladder and disconnects when EN is pulled low; short to VS if the internal switch is unused. |
| 4 | UVLO | input | Adjustable undervoltage threshold input; a resistor divider from SW to UVLO to GND sets the UVLO falling threshold that pulls HGATE low to turn off the HSFET. |
| 5 | OV | input | Adjustable overvoltage threshold input; a resistor divider from SW to OV sets the OV cutoff threshold that pulls HGATE low to turn off the HSFET. |
| 6 | EN | input | Enable input, typically tied to VS for always-on operation or driven externally; pulling it below V(ENF) places the device in the low-IQ shutdown mode. |
| 7 | SLEEP | input | Active-low sleep-mode input driven by a microcontroller; pulling it low turns off the charge pump and gate drivers and powers the output through an internal current-limited bypass switch. |
| 8 | NC | unconnected | No internal connection. |
| 9 | TMR | input | Fault timer input; a capacitor from TMR to GND sets the overcurrent-warning, fault (FLT), and retry timing, leaving it open sets the fastest timing, and tying it to GND disables overcurrent protection. |
| 10 | IMON | output | Analog current-monitor output that sources a scaled current through the external RSNS sense resistor; an external resistor to GND converts this current to a proportional voltage, and the pin should float if unused. |
| 11 | ILIM | input | Overcurrent detection set pin; a resistor from ILIM to GND sets the overcurrent comparator threshold, and ILIM should be tied to GND if overcurrent protection is not needed. |
| 12 | FLT | output | Open-drain fault output that is pulled low during a UVLO, OV, OCP, or SCP event. |
| 13 | GND | power_in | Ground connection to the system ground plane. |
| 14 | HGATE | output | Gate-drive output for the load-disconnect HSFET; connects to the gate of the external MOSFET (Q2). |
| 15 | OUT | input | Connection to the output power rail (external MOSFET source) used to sense the output voltage for load-disconnect control. |
| 16 | SLEEP_OV | input | Sleep-mode overvoltage protection pin; connect to VS for OV cutoff behavior or to OUT for OV clamp behavior during sleep mode. |
| 17 | NC | unconnected | No internal connection. |
| 18 | ISCP | input | Short-circuit detection threshold set pin; leave floating if short-circuit protection is not needed, or tie to CS+ to set the internal fixed 20 mV threshold. |
| 19 | CS- | input | Negative input of the current-sense amplifier. |
| 20 | CS+ | input | Positive input of the current-sense amplifier; connect a 50 to 100 mΩ resistor between CS+ and the external current-sense resistor. |
| 21 | NC | unconnected | No internal connection. |
| 22 | VS | power_in | IC input power supply; connect VS to the mid-point of the common-drain back-to-back MOSFET configuration and place a 100 nF capacitor between VS and GND. |
| 23 | CAP | output | Charge-pump output; place a 100 nF capacitor between CAP and VS to supply the gate-drive charge pump. |
| 24 | C | input | Cathode of the ideal diode; connects to the drain of the external MOSFET (Q1). |
| 25 | RTN | unconnected | Exposed thermal pad; keep it floating and do not connect it to the GND plane. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24-EP(4x4) |
| Category | Power Management (PMIC) |
| Pins | 25 |
CAD (KiCad official)
- Symbol:
LM74910QRGERQ1 - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
lm74910qrgerq1-etched.step/lm74910qrgerq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm74910qrgerq1.step/lm74910qrgerq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (50 pp, sha256
0dec8e92d6d855bd, retrieved 2026-09-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).