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LM63625DQPWPRQ1

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Texas Instruments DC-DC Converters, HTSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs lm63625dqpwprq1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
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lm63625dqpwprq1-etched.fit.json lm63625dqpwprq1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
lm63625dqpwprq1-etched.glb lm63625dqpwprq1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
lm63625dqpwprq1-etched.step lm63625dqpwprq1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
lm63625dqpwprq1.glb Publish 0.1.0 · Ray 1mo ago
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lm63625dqpwprq1.step Publish 0.1.0 · Ray 1mo ago
package.json lm63625dqpwprq1: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
page.json lm63625dqpwprq1: specified limits as data (metadata.characteristics, 52 rows from the datasheet) · Ray 25d ago
README.md lm63625dqpwprq1: specified limits as data (metadata.characteristics, 52 rows from the datasheet) · Ray 25d ago

LM63625DQPWPRQ1

Texas Instruments · DC-DC Converters · HTSSOP-16-EP

LM63625DQPWPRQ1 from Texas Instruments, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SW power_out Regulator switching node; connect to power inductor; supports voltage swing -6V to +40V transient with rise/fall times <10ns.
2 SW power_out Regulator switching node duplicate connection; connect to power inductor; voltage range -6V to +40V transient.
3 CBOOT power_in Bootstrap supply voltage for internal high-side MOSFET gate driver; connect 220nF quality ceramic capacitor between CBOOT and SW pin; UVLO threshold 2.13V.
4 VCC power_out Internal 5V LDO regulated output for control circuit supply; connect 1µF quality capacitor to PGND; output voltage 4.75V to 5.25V nominal; do not connect external loads.
5 RT input Frequency programming input; connect to VCC for 400kHz, connect to AGND for 2.1MHz, or connect to external resistor for adjustable 250kHz to 2200kHz switching frequency; cannot be left floating.
6 VSEL input Output voltage selection input; connect to VCC for 5V fixed output, connect to AGND for 3.3V fixed output, or connect 10kΩ resistor to AGND for adjustable output 1V to 20V; cannot be left floating.
7 SYNC/MODE input Mode selection and external synchronization clock input; connect to VCC for forced PWM mode, connect to AGND for automatic PFM/PWM mode, or apply external clock 250kHz to 2200kHz for synchronized operation; includes 100kΩ internal pull-down.
8 RESET output Open-drain power good flag output; pulled low when output voltage exceeds ±12% deviation, during soft-start, upon internal fault, or when EN input is low; connect through 10kΩ to 100kΩ current-limiting resistor to logic supply.
9 FB input Feedback input to output voltage regulation loop; regulated to 1.0V internal reference in adjustable mode, 5.0V in 5V fixed mode, or 3.3V in 3.3V fixed mode; input bias current 0.1µA to 3.4µA depending on mode.
10 AGND power_in Analog ground reference for control circuits; provides common reference point for all internal biasing, feedback measurement, and electrical parameter specifications; connect to PCB system ground.
11 EN input Precision enable input to regulator; voltage ≥1.425V enables soft-start and regulation, voltage ≤0.94V disables converter; cannot be left floating; can be directly connected to VIN or through external divider for custom UVLO threshold.
12 VIN power_in Input power supply rail; accepts 3.5V to 36V input voltage; bypass with 4.7µF quality ceramic capacitor and 220nF capacitor placed within 1mm of VIN and PGND pins; quiescent input current 23µA typical.
13 VIN power_in Input power supply rail duplicate connection; bypass with quality ceramic capacitor; same voltage range 3.5V to 36V and bypass requirements as pin 12.
14 NC unconnected No connection; no internal circuit connection to this pin; leave unconnected; do not apply external voltage.
15 PGND power_in Power ground terminal; source connection for low-side MOSFET switch; connect to system ground and input/output capacitor grounds using short wide traces to minimize loop inductance.
16 PGND power_in Power ground terminal duplicate connection; parallel ground connection for low-impedance distribution of switching stage currents to ground plane.
17 DAP power_in Exposed thermal pad for heatsink and electrical ground connection; provides primary thermal dissipation path and electrical ground; solder directly to PCB ground layer using thermal via matrix for optimal thermal performance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-16-EP
Category Power Management (PMIC)
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
输入电压 VIN 至 PGND VIN 3.5 36 V 6
EN 至 AGND EN 0 36 V 6
SYNC/MODE、VSEL 和 RT 至 AGND SYNC/MODE, VSEL, RT 0 5 V 6
RESET 至 AGND RESET 0 5 V 6
输出电压 VOUT 1 20 V 6
VCC 外部供电 VCC 2.7 5.25 V 6
输出电流 LM63625 IOUT 0 2.5 A LM63625 6
VIN 至 PGND (HTSSOP 封装) VIN -0.3 40 V 6
EN 至 AGND (HTSSOP 封装) EN -0.3 40 V 6
SYNC/MODE 到 AGND SYNC/MODE -0.3 6 V 6
VSEL 和 RT 至 AGND VSEL, RT -0.3 5.5 V 6
RESET 至 AGND RESET -0.3 16 V 6
FB 至 AGND (固定 VOUT 模式) FB -0.3 16 V 固定 VOUT 模式 6
FB 至 AGND (可调 VOUT 模式) FB -0.3 5.5 V 可调 VOUT 模式 6
AGND 到 PGND AGND -0.3 0.3 V 6
SW 至 PGND，瞬变时间不到 10ns (HTSSOP 封装) SW -6 40 V 瞬变时间不到 10ns 6
BOOT 至 SW BOOT -0.3 5.5 V 6
VCC 到 AGND VCC -0.3 5.5 V 6
结温 TJ TJ -40 150 °C 6
贮存温度 Tstg Tstg -65 150 °C 6
结至环境热阻 (HTSSOP 16 引脚) RθJA 43.1 °C/W JESD 51-7, 4 层 JEDEC 板 7
结至外壳（顶部）热阻 (HTSSOP 16 引脚) RθJC(top) 35.4 °C/W 7
结至电路板热阻 (HTSSOP 16 引脚) RθJB 18.5 °C/W 7
结至顶部特征参数 (HTSSOP 16 引脚) ΨJT 0.9 °C/W 7
结至电路板特征参数 (HTSSOP 16 引脚) ΨJB 18.5 °C/W 7
结至外壳（底部）热阻 (HTSSOP 16 引脚) RθJC(bot) 4.5 °C/W 7
短路高侧电流限值 (2.5A 版本) ISC 3.18 3.75 4.41 A 2.5A 版本 8
低侧电流限值 (2.5A 版本) ILS-LIMIT 2.55 3 3.53 A 2.5A 版本 8
最小峰值电感器电流 (2.5A 版本) IPEAK-MIN 0.373 0.65 1 A 2.5A 版本 8
负电流限值 (LM63625, 2.5A 版本) IL-NEG -1.49 -1.2 -0.75 A 2.5A 版本 8
FB 引脚上的断续阈值 VHICCUP 37 42 47 % 8
RESET 阈值上限 - 上升 FB 电压 V RESET-HIGH 110 112 115 % 8
RESET 阈值下限 - 下降 FB 电压 V RESET-LOW 91 93 95 % 8
RESET 迟滞 FB 电压 V RESET-HYS 1.1 1.8 2.5 % 8
正常 PG 功能的最小输入电压 V RESET-VALID 0.7 1.04 1.25 V 在 VRESET 小于 0.4V 且通过 10kΩ 上拉电阻连接至外部 5V 电源的情况下测得 9
RESET 导通电阻 (VEN=5V) RRESET 60 150 Ω VEN = 5V，1mA 上拉电流 9
RESET 导通电阻 (VEN=0V) RRESET 40 125 Ω VEN = 0V，1mA 上拉电流 9
VCC 内部 VCC 电压 VCC 4.75 5 5.25 V 6V ≤ VIN ≤ 最大工作 VIN 8
VCC 钳位电压 VCCM 5.25 5.55 5.8 V 向 VCC 提供 1mA 8
反馈电压 (可调 VOUT) VFB_ADJ 0.985 1 1.015 V VIN = 3.5V – 最大工作 VIN 8
反馈电压 (5V 固定) VFB_5V 4.925 5 5.075 V VIN = 5.5V – 最大工作 VIN 8
反馈电压 (3.3V 固定) VFB_3p3V 3.25 3.3 3.35 V VIN = 3.8V – 最大工作 VIN 8
VOUT 的精密使能高电平 VEN-H 1.425 1.5 1.575 V VEN 上升 8
使能输入泄漏电流 ILKG-EN -100 0.2 300 nA VEN = 13.5V 8
用于选择可调输出电压的电阻器范围 RSEL-ADJ 8 50 kΩ 8
IPOR 触发 OVP 时 SW 上的下拉电流 IPOR 0.5 1.5 2.5 mA VEN = 0V、VSW = 5V 8
最小开关的 tOC 过流断续重试延迟时间 tOC 70 104 140 ms 10
启用断续电流保护之前软启动完成计时器后的时间 tOC_active 11 16 22 ms 10
内部软启动时间 tSS 1 1.6 2.2 ms 10
软启动完成计时器 tSS_DONE 5 8 11 ms 10
RESET 边沿抗尖峰延迟 tdg 10 17 30 µs 10
RESET 运行时间 FB 时间在 RESET 释放前必须有效 tRISE-DELAY 2 3 5 ms 10

CAD (KiCad official)

  • Symbol: LM63625DQPWPRQ1
  • Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
  • 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)
  • 3D model files: lm63625dqpwprq1-etched.step / lm63625dqpwprq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm63625dqpwprq1.step / lm63625dqpwprq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (58 pp, sha256 3be5c04a49a998ff, retrieved 2026-09-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF