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LM5176RHFR

Public Made by Adom

by adom

Texas Instruments DC-DC Controllers, QFN-28-EP(4x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LM5176RHFR

Texas Instruments · DC-DC Controllers · QFN-28-EP(4x5)

LM5176RHFR from Texas Instruments, in a QFN-28-EP(4x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MODE input Current limit hiccup mode selection; 93.1 kΩ to AGND enables hiccup, 200 kΩ or VCC connection disables hiccup.
2 DITH input Frequency dithering enable; external capacitor to AGND modulates oscillator frequency by ±10% for EMI reduction.
3 RT/SYNC input Switching frequency programming pin; external resistor to AGND sets frequency (100-600 kHz) or accepts external clock signal.
4 SLOPE input Slope compensation ramp capacitor connection to AGND; provides ramp for stable current mode operation in buck and boost modes.
5 SS input Soft-start capacitor connection to AGND; capacitor programs soft-start time for gradual VCC and output regulation.
6 COMP output Error amplifier output (0.3 V to 3.0 V range); connect RC compensation network to AGND for feedback loop stability.
7 AGND power_in Analog ground of the IC; reference for all analog circuitry and also accepts PowerPAD solder connection for improved dissipation.
8 FB input Feedback pin for output voltage regulation; connect resistor divider from converter output (0.8 V VREF nominal).
9 VOSNS input Output voltage sense input; monitors power stage output voltage over 0.8-55 V range.
10 ISNS(-) input Current sense amplifier negative input; current sense resistor can locate on input or output side of converter.
11 ISNS(+) input Current sense amplifier positive input; when voltage reaches 50 mV, slow constant current control loop activates for regulation.
12 CSG input PWM current sense amplifier ground reference; connect directly to low-side of current sense resistor.
13 CS input Positive input to PWM current sense amplifier; implements cycle-by-cycle current limiting.
14 PGOOD output Power-good open-drain output (typical 4.2 mA sink); pulled low when FB voltage deviates outside ±9%/+10% of 0.8 V nominal.
15 SW2 input Boost side switching node; external bootstrap capacitor (0.1-0.22 µF ceramic) connects between SW2 and BOOT2.
16 HDRV2 output High-side gate driver output for boost switch; capable of sourcing 1.8 A and sinking 2.2 A peak current to MOSFET gate.
17 BOOT2 power_out Bootstrap power supply connection; external capacitor (0.1-0.22 µF ceramic) required between BOOT2 and SW2 to power HDRV2.
18 LDRV2 output Low-side gate driver output for boost switch; capable of sourcing 1.8 A and sinking 2.2 A peak current from VCC.
19 PGND power_in Power ground of the IC; provides high current ground connection for low-side gate drivers.
20 VCC power_out Internal bias regulator output; connect 0.1 µF capacitor to PGND or accept external 8-36 V supply via BIAS pin when VBIAS > 8 V.
21 BIAS power_in Optional external bias supply input (8-36 V); reduces IC power loss at high VIN when VBIAS exceeds 8 V threshold.
22 LDRV1 output Low-side gate driver output for buck switch; capable of sourcing 1.8 A and sinking 2.2 A peak current from VCC.
23 BOOT1 power_out Bootstrap power supply connection; external capacitor (0.1-0.22 µF ceramic) required between BOOT1 and SW1 to power HDRV1.
24 HDRV1 output High-side gate driver output for buck switch; capable of sourcing 1.8 A and sinking 2.2 A peak current to MOSFET gate.
25 SW1 input Buck side switching node; external bootstrap capacitor (0.1-0.22 µF ceramic) connects between SW1 and BOOT1.
26 EN/UVLO input Enable and under-voltage lockout input; below 0.4 V enters shutdown, above 1.22 V enables PWM if VCC exceeds UV threshold.
27 VIN power_in Input supply voltage pin; accepts 4.2-55 V nominal (maximum 60 V transient); 2.5-55 V with external BIAS ≥ 5 V.
28 VISNS input Input voltage sense pin; monitors power stage input rail voltage, valid 2.5-55 V range with VBIAS ≥ 5 V or VIN ≥ 4.5 V.
29 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-28-EP(4x5)
Category Power Supply Chip
Pins 29

CAD (KiCad official)

  • Symbol: LM5176RHFR
  • Footprint: Package_DFN_QFN:QFN-28-1EP_4x5mm_P0.5mm_EP2.65x3.65mm
  • 3D model: QFN-28-EP(4x5) (KiCad packages3D, STEP)
  • 3D model files: lm5176rhfr-etched.step / lm5176rhfr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm5176rhfr.step / lm5176rhfr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (46 pp, sha256 4ce39346e67c6561, retrieved 2026-10-05, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF