component
LM5176RHFR
Public Made by Adomby adom
Texas Instruments DC-DC Controllers, QFN-28-EP(4x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+66@@ -0,0 +1,66 @@+# LM5176RHFR++**Texas Instruments** · DC-DC Controllers · QFN-28-EP(4x5)++LM5176RHFR from Texas Instruments, in a QFN-28-EP(4x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | MODE | input | Current limit hiccup mode selection; 93.1 kΩ to AGND enables hiccup, 200 kΩ or VCC connection disables hiccup. |+| 2 | DITH | input | Frequency dithering enable; external capacitor to AGND modulates oscillator frequency by ±10% for EMI reduction. |+| 3 | RT/SYNC | input | Switching frequency programming pin; external resistor to AGND sets frequency (100-600 kHz) or accepts external clock signal. |+| 4 | SLOPE | input | Slope compensation ramp capacitor connection to AGND; provides ramp for stable current mode operation in buck and boost modes. |+| 5 | SS | input | Soft-start capacitor connection to AGND; capacitor programs soft-start time for gradual VCC and output regulation. |+| 6 | COMP | output | Error amplifier output (0.3 V to 3.0 V range); connect RC compensation network to AGND for feedback loop stability. |+| 7 | AGND | power_in | Analog ground of the IC; reference for all analog circuitry and also accepts PowerPAD solder connection for improved dissipation. |+| 8 | FB | input | Feedback pin for output voltage regulation; connect resistor divider from converter output (0.8 V VREF nominal). |+| 9 | VOSNS | input | Output voltage sense input; monitors power stage output voltage over 0.8-55 V range. |+| 10 | ISNS(-) | input | Current sense amplifier negative input; current sense resistor can locate on input or output side of converter. |+| 11 | ISNS(+) | input | Current sense amplifier positive input; when voltage reaches 50 mV, slow constant current control loop activates for regulation. |+| 12 | CSG | input | PWM current sense amplifier ground reference; connect directly to low-side of current sense resistor. |+| 13 | CS | input | Positive input to PWM current sense amplifier; implements cycle-by-cycle current limiting. |+| 14 | PGOOD | output | Power-good open-drain output (typical 4.2 mA sink); pulled low when FB voltage deviates outside ±9%/+10% of 0.8 V nominal. |+| 15 | SW2 | input | Boost side switching node; external bootstrap capacitor (0.1-0.22 µF ceramic) connects between SW2 and BOOT2. |+| 16 | HDRV2 | output | High-side gate driver output for boost switch; capable of sourcing 1.8 A and sinking 2.2 A peak current to MOSFET gate. |+| 17 | BOOT2 | power_out | Bootstrap power supply connection; external capacitor (0.1-0.22 µF ceramic) required between BOOT2 and SW2 to power HDRV2. |+| 18 | LDRV2 | output | Low-side gate driver output for boost switch; capable of sourcing 1.8 A and sinking 2.2 A peak current from VCC. |+| 19 | PGND | power_in | Power ground of the IC; provides high current ground connection for low-side gate drivers. |+| 20 | VCC | power_out | Internal bias regulator output; connect 0.1 µF capacitor to PGND or accept external 8-36 V supply via BIAS pin when VBIAS > 8 V. |+| 21 | BIAS | power_in | Optional external bias supply input (8-36 V); reduces IC power loss at high VIN when VBIAS exceeds 8 V threshold. |+| 22 | LDRV1 | output | Low-side gate driver output for buck switch; capable of sourcing 1.8 A and sinking 2.2 A peak current from VCC. |+| 23 | BOOT1 | power_out | Bootstrap power supply connection; external capacitor (0.1-0.22 µF ceramic) required between BOOT1 and SW1 to power HDRV1. |+| 24 | HDRV1 | output | High-side gate driver output for buck switch; capable of sourcing 1.8 A and sinking 2.2 A peak current to MOSFET gate. |+| 25 | SW1 | input | Buck side switching node; external bootstrap capacitor (0.1-0.22 µF ceramic) connects between SW1 and BOOT1. |+| 26 | EN/UVLO | input | Enable and under-voltage lockout input; below 0.4 V enters shutdown, above 1.22 V enables PWM if VCC exceeds UV threshold. |+| 27 | VIN | power_in | Input supply voltage pin; accepts 4.2-55 V nominal (maximum 60 V transient); 2.5-55 V with external BIAS ≥ 5 V. |+| 28 | VISNS | input | Input voltage sense pin; monitors power stage input rail voltage, valid 2.5-55 V range with VBIAS ≥ 5 V or VIN ≥ 4.5 V. |+| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | QFN-28-EP(4x5) |+| Category | Power Supply Chip |+| Pins | 29 |++## CAD (KiCad official)++- Symbol: `LM5176RHFR`+- Footprint: `Package_DFN_QFN:QFN-28-1EP_4x5mm_P0.5mm_EP2.65x3.65mm`+- 3D model: QFN-28-EP(4x5) (KiCad packages3D, STEP)+- 3D model files: `lm5176rhfr-etched.step` / `lm5176rhfr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lm5176rhfr.step` / `lm5176rhfr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lm5176) (46 pp, sha256 `4ce39346e67c6561`, retrieved 2026-10-05, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/lm5176rhfr-datasheet.pdf)
page.jsonadded+287@@ -0,0 +1,287 @@+{+ "slug": "lm5176rhfr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments DC-DC Controllers, QFN-28-EP(4x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power supply chip",+ "lm5176rhfr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "lm5176rhfr.kicad_sym",+ "lm5176rhfr.kicad_mod",+ "lm5176rhfr.glb",+ "lm5176rhfr.step",+ "lm5176rhfr.lbr",+ "docs/hero.png",+ "docs/lm5176rhfr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "lm5176rhfr-hero.glb",+ "lm5176rhfr-hero.overlay.json"+ ],+ "component": {+ "mpn": "LM5176RHFR",+ "manufacturer": "Texas Instruments",+ "package": "QFN-28-EP(4x5)",+ "pin_count": 29,+ "category": "Power Supply Chip",+ "subcategory": "DC-DC Controllers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/lm5176",+ "parts": {+ "symbol": "lm5176rhfr.kicad_sym",+ "footprint": "lm5176rhfr.kicad_mod",+ "model_3d": "lm5176rhfr-hero.glb",+ "model_3d_plain": "lm5176rhfr.glb",+ "model_3d_step": "lm5176rhfr-etched.step",+ "model_3d_step_plain": "lm5176rhfr.step",+ "lbr": "lm5176rhfr.lbr"+ },+ "distributor_links": {+ "lcsc": 1850330,+ "digikey": "296-LM5176RHFRTR-ND",+ "mouser": "595-LM5176RHFR"+ },+ "distributor_check": {+ "checked_at": "2026-10-05T19:53:06Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-LM5176RHFRTR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-LM5176RHFR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "MODE",+ "type": "input",+ "description": "Current limit hiccup mode selection; 93.1 kΩ to AGND enables hiccup, 200 kΩ or VCC connection disables hiccup."+ },+ {+ "number": "2",+ "name": "DITH",+ "type": "input",+ "description": "Frequency dithering enable; external capacitor to AGND modulates oscillator frequency by ±10% for EMI reduction."+ },+ {+ "number": "3",+ "name": "RT/SYNC",+ "type": "input",+ "description": "Switching frequency programming pin; external resistor to AGND sets frequency (100-600 kHz) or accepts external clock signal."+ },+ {+ "number": "4",+ "name": "SLOPE",+ "type": "input",+ "description": "Slope compensation ramp capacitor connection to AGND; provides ramp for stable current mode operation in buck and boost modes."+ },+ {+ "number": "5",+ "name": "SS",+ "type": "input",+ "description": "Soft-start capacitor connection to AGND; capacitor programs soft-start time for gradual VCC and output regulation."+ },+ {+ "number": "6",+ "name": "COMP",+ "type": "output",+ "description": "Error amplifier output (0.3 V to 3.0 V range); connect RC compensation network to AGND for feedback loop stability."+ },+ {+ "number": "7",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground of the IC; reference for all analog circuitry and also accepts PowerPAD solder connection for improved dissipation."+ },+ {+ "number": "8",+ "name": "FB",+ "type": "input",+ "description": "Feedback pin for output voltage regulation; connect resistor divider from converter output (0.8 V VREF nominal)."+ },+ {+ "number": "9",+ "name": "VOSNS",+ "type": "input",+ "description": "Output voltage sense input; monitors power stage output voltage over 0.8-55 V range."+ },+ {+ "number": "10",+ "name": "ISNS(-)",+ "type": "input",+ "description": "Current sense amplifier negative input; current sense resistor can locate on input or output side of converter."+ },+ {+ "number": "11",+ "name": "ISNS(+)",+ "type": "input",+ "description": "Current sense amplifier positive input; when voltage reaches 50 mV, slow constant current control loop activates for regulation."+ },+ {+ "number": "12",+ "name": "CSG",+ "type": "input",+ "description": "PWM current sense amplifier ground reference; connect directly to low-side of current sense resistor."+ },+ {+ "number": "13",+ "name": "CS",+ "type": "input",+ "description": "Positive input to PWM current sense amplifier; implements cycle-by-cycle current limiting."+ },+ {+ "number": "14",+ "name": "PGOOD",+ "type": "output",+ "description": "Power-good open-drain output (typical 4.2 mA sink); pulled low when FB voltage deviates outside ±9%/+10% of 0.8 V nominal."+ },+ {+ "number": "15",+ "name": "SW2",+ "type": "input",+ "description": "Boost side switching node; external bootstrap capacitor (0.1-0.22 µF ceramic) connects between SW2 and BOOT2."+ },+ {+ "number": "16",+ "name": "HDRV2",+ "type": "output",+ "description": "High-side gate driver output for boost switch; capable of sourcing 1.8 A and sinking 2.2 A peak current to MOSFET gate."+ },+ {+ "number": "17",+ "name": "BOOT2",+ "type": "power_out",+ "description": "Bootstrap power supply connection; external capacitor (0.1-0.22 µF ceramic) required between BOOT2 and SW2 to power HDRV2."+ },+ {+ "number": "18",+ "name": "LDRV2",+ "type": "output",+ "description": "Low-side gate driver output for boost switch; capable of sourcing 1.8 A and sinking 2.2 A peak current from VCC."+ },+ {+ "number": "19",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground of the IC; provides high current ground connection for low-side gate drivers."+ },+ {+ "number": "20",+ "name": "VCC",+ "type": "power_out",+ "description": "Internal bias regulator output; connect 0.1 µF capacitor to PGND or accept external 8-36 V supply via BIAS pin when VBIAS > 8 V."+ },+ {+ "number": "21",+ "name": "BIAS",+ "type": "power_in",+ "description": "Optional external bias supply input (8-36 V); reduces IC power loss at high VIN when VBIAS exceeds 8 V threshold."+ },+ {+ "number": "22",+ "name": "LDRV1",+ "type": "output",+ "description": "Low-side gate driver output for buck switch; capable of sourcing 1.8 A and sinking 2.2 A peak current from VCC."+ },+ {+ "number": "23",+ "name": "BOOT1",+ "type": "power_out",+ "description": "Bootstrap power supply connection; external capacitor (0.1-0.22 µF ceramic) required between BOOT1 and SW1 to power HDRV1."+ },+ {+ "number": "24",+ "name": "HDRV1",+ "type": "output",+ "description": "High-side gate driver output for buck switch; capable of sourcing 1.8 A and sinking 2.2 A peak current to MOSFET gate."+ },+ {+ "number": "25",+ "name": "SW1",+ "type": "input",+ "description": "Buck side switching node; external bootstrap capacitor (0.1-0.22 µF ceramic) connects between SW1 and BOOT1."+ },+ {+ "number": "26",+ "name": "EN/UVLO",+ "type": "input",+ "description": "Enable and under-voltage lockout input; below 0.4 V enters shutdown, above 1.22 V enables PWM if VCC exceeds UV threshold."+ },+ {+ "number": "27",+ "name": "VIN",+ "type": "power_in",+ "description": "Input supply voltage pin; accepts 4.2-55 V nominal (maximum 60 V transient); 2.5-55 V with external BIAS ≥ 5 V."+ },+ {+ "number": "28",+ "name": "VISNS",+ "type": "input",+ "description": "Input voltage sense pin; monitors power stage input rail voltage, valid 2.5-55 V range with VBIAS ≥ 5 V or VIN ≥ 4.5 V."+ },+ {+ "number": "29",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: SW1 and SW2 marked as input (I) in datasheet table, but functionally represent switching node output; PGOOD described as open-drain output; in strict KiCad ERC, open-drain should be tri_state rather tha; PowerPAD (exposed pad) should be soldered to AGND but is not assigned a pin number 1-28; requires se",+ "exposed pad 29 added from the footprint"+ ],+ "pages_sent": 12,+ "cost_usd": 0.2097,+ "at": "2026-10-05T19:52:50"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/lm5176",+ "pages": 46,+ "sha256": "4ce39346e67c6561",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 29,+ "described": 29,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}