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LM5141QRGERQ1

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Texas Instruments DC-DC Converters, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs lm5141qrgerq1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers lm5141qrgerq1: viewers · Ray 1mo ago
lm5141qrgerq1-etched.fit.json lm5141qrgerq1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
lm5141qrgerq1-etched.glb lm5141qrgerq1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
lm5141qrgerq1-etched.step lm5141qrgerq1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
lm5141qrgerq1.glb Publish 0.1.0 · Ray 1mo ago
lm5141qrgerq1.kicad_mod Publish 0.1.0 · Ray 1mo ago
lm5141qrgerq1.kicad_sym Publish 0.1.0 · Ray 1mo ago
lm5141qrgerq1.lbr Publish 0.1.0 · Ray 1mo ago
lm5141qrgerq1.step Publish 0.1.0 · Ray 1mo ago
package.json lm5141qrgerq1: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
page.json lm5141qrgerq1: specified limits as data (metadata.characteristics, 60 rows from the datasheet) · Ray 26d ago
README.md lm5141qrgerq1: specified limits as data (metadata.characteristics, 60 rows from the datasheet) · Ray 26d ago

LM5141QRGERQ1

Texas Instruments · DC-DC Converters · VQFN-24-EP(4x4)

LM5141QRGERQ1 from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DEMB input Diode emulation or external synchronization clock input (350 kHz to 550 kHz at 440 kHz, 1.8 MHz to 2.6 MHz at 2.2 MHz); connect to AGND for diode emulation or VDDA for forced PWM mode.
2 VDDA power_out Internal analog bias regulator output (4.75 V to 5.25 V typical 5 V); bypass with 100 nF or greater ceramic capacitor to AGND.
3 AGND power_in Analog ground connection for internal voltage reference and analog circuits; connect to PGND at single point under IC.
4 RT input Resistor to ground shifts oscillator frequency (1.8 to 2.53 MHz for 2.2 MHz mode, 300 to 500 kHz for 440 kHz mode); analog voltage 0 to 0.6 V modulates frequency.
5 DITH output Dither output for frequency spread spectrum; capacitor to AGND modulates frequency ±5% with 20 µA source/sink current; connect to VDDA to disable.
6 OSC input Oscillator frequency selection input; connect to VDDA for 2.2 MHz operation or AGND for 440 kHz operation (state latched during VCC power-up).
7 LOL output Low-side gate driver turnoff output with peak sink current 4.25 A; rise/fall time 4 ns with 2700 pF load.
8 LO output Low-side gate driver turnon output with peak source current 3.25 A; rise/fall time 4 ns with 2700 pF load.
9 PGND power_in Power ground connection pin for low-side gate driver; connect to power ground plane.
10 VCC power_out VCC bias supply (4.75 V to 5.25 V) with 75 mA to 125 mA sourcing current limit; bypass with 2.2 µF to 4.7 µF capacitor to PGND.
11 HB power_out High-side bootstrap supply (5 V to 5.25 V nominal); charged through external diode when SW low with 3 µA quiescent current and 2.5 V UVLO threshold.
12 SW input Switching node connecting bootstrap capacitor, high-side MOSFET source, and low-side MOSFET drain; monitored by IC for adaptive dead-time control with -5 mV zero-crossing threshold.
13 HO output High-side gate driver turnon output with peak source current 3.25 A (at VHO = 0 V, SW = 0 V, HB = 5 V).
14 HOL output High-side gate driver turnoff output with peak sink current 4.25 A; rise/fall time 4 ns with 2700 pF load.
15 VIN power_in Main supply voltage input (3.8 V to 65 V steady-state, 70 V absolute maximum); source for internal VCC regulator and charge pump.
16 VCCX power_in Optional external bias supply input; if VCCX > 4.5 V, internal VCC regulator is disabled (maximum 6.5 V); ground if unused.
17 VOUT input Current sense amplifier inverting input connected to output side of current-sense resistor (1.5 V to 15 V) with gain 12 V/V.
18 CS input Current sense amplifier non-inverting input with 75 mV current-limit threshold; use Kelvin connection to inductor side of sense resistor.
19 FB input Feedback pin with 1.2 V regulation threshold; connect to VDDA for 3.3 V output, AGND for 5 V output, or external divider for 1.5 V to 15 V adjustable output.
20 COMP input Compensation pin for transconductance error amplifier output (1200 µS gain) enabling external type II control loop compensation network.
21 PG output Open-collector power-good output; pulls low when VOUT outside 92% to 110% window with 25 µs overvoltage and 30 µs undervoltage filter delays.
22 SS input Soft-start programming pin; external capacitor and internal 20 µA current source set voltage ramp rate; pulling below 80 mV disables gate driver outputs.
23 EN input Active-high logic enable input (up to 70 V); enabled when EN > 2 V, shutdown when EN < 0.8 V with 10 µA typical shutdown current.
24 RES output Restart timer output; external capacitor and 20 µA current source configure hiccup mode; charges to 1.2 V threshold to restart after 512 consecutive current-limit cycles.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(4x4)
Category Power Management (PMIC)
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VIN -0.3 70 V 4
SW to PGND SW to PGND -0.3 70 V 4
SW to PGND transient SW to PGND -5 V 20 ns transient 4
HB to SW HB to SW -0.3 6.5 V 4
HB to SW transient HB to SW -5 V 20 ns transient 4
HO, HOL to SW transient HO, HOL to SW -5 V 20 ns transient 4
LO, LOL to PGND transient LO, LOL to PGND -1.5 V 20 ns transient 4
EN to PGND EN to PGND -0.3 70 V 4
VCC, VCCX, VDD, PG, FB VCC, VCCX, VDD, PG, FB -0.3 6.5 V 4
VOUT, CS VOUT, CS -0.3 15.5 V 4
PGND to AGND PGND to AGND -0.3 0.3 V 4
Operating junction temperature TJ -40 150 °C 4
Storage temperature Tstg -65 150 °C 4
Input voltage VIN 3.8 65 V 5
SW to PGND SW to PGND -0.3 65 V 5
HB to SW HB to SW -0.3 5 5.25 V 5
LO, LOL to PGND LO, LOL to PGND -0.3 5 5.25 V 5
FB, PG, OSC, SS, RES, DEMB, VCCX FB, PG, OSC, SS, RES, DEMB, VCCX -0.3 5 V 5
EN to PGND EN to PGND -0.3 65 V 5
VCC, VDD VCC, VDD -0.3 5 5.25 V 5
VOUT, CS VOUT, CS 1.5 5 15 V 5
PGND to AGND PGND to AGND -0.3 0.3 V 5
Operating junction temperature TJ -40 150 °C 5
Shutdown mode current ISHUTDOWN 10 12.5 µA VIN = 8–18 V, EN = 0 V, VCCX = 0 V 6
Standby current ISTANDBY 35 45 µA EN = 5 V, FB = VDD, VOUT in regulation, no-load, not switching, DEMB = GND 6
Standby current ISTANDBY 42 55 µA EN = 5 V, FB = 0 V, VOUT in regulation, no-load, not switching, VCCX = 5 V, DEMB = GND 6
VCC regulation voltage VCC(REG) 4.75 5 5.25 V VIN = 6 to 18 V, 0 to 75 mA, VCCX = 0 V 6
VCC undervoltage threshold VCC(UVLO) 3.25 3.4 3.55 V VCC rising, VCCX = 0 V 6
VCC sourcing current limit ICC(LIM) 85 125 mA VCCX = 0 V 6
Internal bias supply power VDDA(REG) 4.75 5 5.25 V VCCX = 0 V 6
VDDA undervoltage threshold VDDA(UVLO) 3.1 3.2 3.3 V VCC rising, VCCX = 0 V 6
VCCX on threshold VCCX(ON) 4.1 4.3 4.4 V VCC rising 6
Current limit threshold V(CS) 68 75 82 mV ILSET = VDDA, measure from CS to VOUT 6
Current sense amplifier gain Gain 11.4 12 12.6 V/V 6
3.3 V output voltage regulation VOUT 3.273 3.3 3.327 V VIN = 3.8 to 42 V 6
5 V output voltage regulation VOUT 4.96 5 5.04 V VIN = 5.5 to 42 V 6
Regulated feedback voltage VFB 1.193 1.2 1.207 V 6
PG undervoltage trip level PG(UV) 90 92 94 % Falling with respect to the regulation voltage 7
PG overvoltage trip level PG(OVP) 108 110 112 % Rising with respect to the regulation voltage 7
Transconductance gain, feedback to COMP Gm 1010 1200 µS Feedback to COMP 7
HO off to LO on dead time tdly1 20 40 ns 7
LO off to HO on dead time tdly2 20 38 ns 7
DEMB input low frequency range fDEMB 350 550 kHz 440 kHz 8
DEMB input high frequency range fDEMB 1800 2600 kHz 2.2 MHz 8
Soft-start current ISS 16 22 28 µA 8
Oscillator frequency 2.2 MHz fSW 2100 2200 2300 kHz OSC = VDDA, VIN = 8–18 V 8
Oscillator frequency 440 kHz fSW 420 440 460 kHz OSC = GND, VIN = 8–18 V 8
RT adjustment range minimum, 2.2 MHz fSW 1710 1800 1890 kHz OSC = VDD, RTMIN = 61.9 kΩ 8
RT adjustment range typical, 2.2 MHz fSW 2100 2200 2300 kHz OSC = VDD, RTTYP = 49.9 kΩ 8
RT adjustment range maximum, 2.2 MHz fSW 2405 2530 2655 kHz OSC = VDD, RTMAX = 43.2 kΩ 8
RT adjustment range minimum, 440 kHz fSW 285 300 315 kHz OSC = GND, RTMIN = 73.2 kΩ 8
RT adjustment range typical, 440 kHz fSW 420 440 460 kHz OSC = GND, RTTYP = 49.9 kΩ 8
RT adjustment range maximum, 440 kHz fSW 475 500 525 kHz OSC = GND, RTMAX = 44.2 kΩ 8
Minimum on-time ton 45 66 ns 8
Junction-to-ambient thermal resistance RθJA 34.1 °C/W 5
Junction-to-case (top) thermal resistance RθJC(top) 36.8 °C/W 5
Junction-to-board thermal resistance RθJB 12.1 °C/W 5
Junction-to-top characterization parameter ψJT 0.5 °C/W 5
Junction-to-board characterization parameter ψJB 12.2 °C/W 5
Junction-to-case (bottom) thermal resistance RθJC(bot) 2.9 °C/W 5

CAD (KiCad official)

  • Symbol: LM5141QRGERQ1
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: lm5141qrgerq1-etched.step / lm5141qrgerq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm5141qrgerq1.step / lm5141qrgerq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (48 pp, sha256 2899e0c97e37baaf, retrieved 2026-09-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF