component
LM5141QRGERQ1
Public Made by Adomby adom
Texas Instruments DC-DC Converters, VQFN-24-EP(4x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLM5141QRGERQ1
Texas Instruments · DC-DC Converters · VQFN-24-EP(4x4)
LM5141QRGERQ1 from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DEMB | input | Diode emulation or external synchronization clock input (350 kHz to 550 kHz at 440 kHz, 1.8 MHz to 2.6 MHz at 2.2 MHz); connect to AGND for diode emulation or VDDA for forced PWM mode. |
| 2 | VDDA | power_out | Internal analog bias regulator output (4.75 V to 5.25 V typical 5 V); bypass with 100 nF or greater ceramic capacitor to AGND. |
| 3 | AGND | power_in | Analog ground connection for internal voltage reference and analog circuits; connect to PGND at single point under IC. |
| 4 | RT | input | Resistor to ground shifts oscillator frequency (1.8 to 2.53 MHz for 2.2 MHz mode, 300 to 500 kHz for 440 kHz mode); analog voltage 0 to 0.6 V modulates frequency. |
| 5 | DITH | output | Dither output for frequency spread spectrum; capacitor to AGND modulates frequency ±5% with 20 µA source/sink current; connect to VDDA to disable. |
| 6 | OSC | input | Oscillator frequency selection input; connect to VDDA for 2.2 MHz operation or AGND for 440 kHz operation (state latched during VCC power-up). |
| 7 | LOL | output | Low-side gate driver turnoff output with peak sink current 4.25 A; rise/fall time 4 ns with 2700 pF load. |
| 8 | LO | output | Low-side gate driver turnon output with peak source current 3.25 A; rise/fall time 4 ns with 2700 pF load. |
| 9 | PGND | power_in | Power ground connection pin for low-side gate driver; connect to power ground plane. |
| 10 | VCC | power_out | VCC bias supply (4.75 V to 5.25 V) with 75 mA to 125 mA sourcing current limit; bypass with 2.2 µF to 4.7 µF capacitor to PGND. |
| 11 | HB | power_out | High-side bootstrap supply (5 V to 5.25 V nominal); charged through external diode when SW low with 3 µA quiescent current and 2.5 V UVLO threshold. |
| 12 | SW | input | Switching node connecting bootstrap capacitor, high-side MOSFET source, and low-side MOSFET drain; monitored by IC for adaptive dead-time control with -5 mV zero-crossing threshold. |
| 13 | HO | output | High-side gate driver turnon output with peak source current 3.25 A (at VHO = 0 V, SW = 0 V, HB = 5 V). |
| 14 | HOL | output | High-side gate driver turnoff output with peak sink current 4.25 A; rise/fall time 4 ns with 2700 pF load. |
| 15 | VIN | power_in | Main supply voltage input (3.8 V to 65 V steady-state, 70 V absolute maximum); source for internal VCC regulator and charge pump. |
| 16 | VCCX | power_in | Optional external bias supply input; if VCCX > 4.5 V, internal VCC regulator is disabled (maximum 6.5 V); ground if unused. |
| 17 | VOUT | input | Current sense amplifier inverting input connected to output side of current-sense resistor (1.5 V to 15 V) with gain 12 V/V. |
| 18 | CS | input | Current sense amplifier non-inverting input with 75 mV current-limit threshold; use Kelvin connection to inductor side of sense resistor. |
| 19 | FB | input | Feedback pin with 1.2 V regulation threshold; connect to VDDA for 3.3 V output, AGND for 5 V output, or external divider for 1.5 V to 15 V adjustable output. |
| 20 | COMP | input | Compensation pin for transconductance error amplifier output (1200 µS gain) enabling external type II control loop compensation network. |
| 21 | PG | output | Open-collector power-good output; pulls low when VOUT outside 92% to 110% window with 25 µs overvoltage and 30 µs undervoltage filter delays. |
| 22 | SS | input | Soft-start programming pin; external capacitor and internal 20 µA current source set voltage ramp rate; pulling below 80 mV disables gate driver outputs. |
| 23 | EN | input | Active-high logic enable input (up to 70 V); enabled when EN > 2 V, shutdown when EN < 0.8 V with 10 µA typical shutdown current. |
| 24 | RES | output | Restart timer output; external capacitor and 20 µA current source configure hiccup mode; charges to 1.2 V threshold to restart after 512 consecutive current-limit cycles. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24-EP(4x4) |
| Category | Power Management (PMIC) |
| Pins | 25 |
CAD (KiCad official)
- Symbol:
LM5141QRGERQ1 - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
lm5141qrgerq1-etched.step/lm5141qrgerq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm5141qrgerq1.step/lm5141qrgerq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (48 pp, sha256
2899e0c97e37baaf, retrieved 2026-09-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).