LM5141QRGERQ1

@@ -77,7 +77,7 @@         "number": "5",         "name": "DITH",         "type": "output",-        "description": "Dither output for frequency spread spectrum; capacitor to AGND modulates frequency \u00b15% with 20 \u00b5A source/sink current; connect to VDDA to disable."+        "description": "Dither output for frequency spread spectrum; capacitor to AGND modulates frequency ±5% with 20 µA source/sink current; connect to VDDA to disable."       },       {         "number": "6",@@ -107,13 +107,13 @@         "number": "10",         "name": "VCC",         "type": "power_out",-        "description": "VCC bias supply (4.75 V to 5.25 V) with 75 mA to 125 mA sourcing current limit; bypass with 2.2 \u00b5F to 4.7 \u00b5F capacitor to PGND."+        "description": "VCC bias supply (4.75 V to 5.25 V) with 75 mA to 125 mA sourcing current limit; bypass with 2.2 µF to 4.7 µF capacitor to PGND."       },       {         "number": "11",         "name": "HB",         "type": "power_out",-        "description": "High-side bootstrap supply (5 V to 5.25 V nominal); charged through external diode when SW low with 3 \u00b5A quiescent current and 2.5 V UVLO threshold."+        "description": "High-side bootstrap supply (5 V to 5.25 V nominal); charged through external diode when SW low with 3 µA quiescent current and 2.5 V UVLO threshold."       },       {         "number": "12",@@ -167,31 +167,31 @@         "number": "20",         "name": "COMP",         "type": "input",-        "description": "Compensation pin for transconductance error amplifier output (1200 \u00b5S gain) enabling external type II control loop compensation network."+        "description": "Compensation pin for transconductance error amplifier output (1200 µS gain) enabling external type II control loop compensation network."       },       {         "number": "21",         "name": "PG",         "type": "output",-        "description": "Open-collector power-good output; pulls low when VOUT outside 92% to 110% window with 25 \u00b5s overvoltage and 30 \u00b5s undervoltage filter delays."+        "description": "Open-collector power-good output; pulls low when VOUT outside 92% to 110% window with 25 µs overvoltage and 30 µs undervoltage filter delays."       },       {         "number": "22",         "name": "SS",         "type": "input",-        "description": "Soft-start programming pin; external capacitor and internal 20 \u00b5A current source set voltage ramp rate; pulling below 80 mV disables gate driver outputs."+        "description": "Soft-start programming pin; external capacitor and internal 20 µA current source set voltage ramp rate; pulling below 80 mV disables gate driver outputs."       },       {         "number": "23",         "name": "EN",         "type": "input",-        "description": "Active-high logic enable input (up to 70 V); enabled when EN > 2 V, shutdown when EN < 0.8 V with 10 \u00b5A typical shutdown current."+        "description": "Active-high logic enable input (up to 70 V); enabled when EN > 2 V, shutdown when EN < 0.8 V with 10 µA typical shutdown current."       },       {         "number": "24",         "name": "RES",         "type": "output",-        "description": "Restart timer output; external capacitor and 20 \u00b5A current source configure hiccup mode; charges to 1.2 V threshold to restart after 512 consecutive current-limit cycles."+        "description": "Restart timer output; external capacitor and 20 µA current source configure hiccup mode; charges to 1.2 V threshold to restart after 512 consecutive current-limit cycles."       },       {         "number": "25",@@ -232,6 +232,46 @@     "viewers": {       "symbol": "viewers/symbol.html",       "footprint": "viewers/footprint.html"-    }+    },+    "models_3d": [+      {+        "file": "lm5141qrgerq1.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          4.0,+          4.0,+          0.77+        ],+        "zmin_mm": 0.0,+        "centre_offset_mm": 0.0,+        "footprint_binding": "identity",+        "sha256": "096fc110543e6d324c5120c2d38e3dca87a389da9b6fac234f1fe40856295ef4",+        "checked": "2026-10-07",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "lm5141qrgerq1-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          4.0,+          4.0,+          0.77+        ],+        "zmin_mm": 0.0,+        "centre_offset_mm": 0.0,+        "footprint_binding": "identity",+        "sha256": "b402ae7f414378d328b26803155501ac13217426b942afe4a749231bbd0985f3",+        "checked": "2026-10-07",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      }+    ]   }-}\ No newline at end of file+}