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LM46002AQPWPTQ1
Public Made by Adomby adom
Texas Instruments DC-DC Converters, HTSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LM46002AQPWPTQ1
Texas Instruments · DC-DC Converters · HTSSOP-16-EP
LM46002AQPWPTQ1 from Texas Instruments, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | power_out | Switching output of the regulator, internally connected to both power MOSFETs, and connected to the power inductor. |
| 2 | SW | power_out | Switching output of the regulator, internally connected to both power MOSFETs, and connected to the power inductor. |
| 3 | CBOOT | power_out | Bootstrap capacitor connection for the high-side driver; connect a high-quality 470-nF capacitor from CBOOT to SW. |
| 4 | VCC | power_out | Internal bias supply output for bypassing; connect a bypass capacitor to AGND, do not connect an external load, and never short it to ground during operation. |
| 5 | BIAS | power_in | Optional internal LDO supply input: tie to VOUT when 3.3 V ≤ VOUT ≤ 28 V (or to an external 3.3-V or 5-V rail), with a 1 to 10 µF bypass capacitor to ground, and tie to ground when not used. |
| 6 | SYNC | input | Clock input to synchronize switching to an external clock, which requires proper high-speed termination to prevent ringing, and connect to ground if not used. |
| 7 | RT | passive | Connect a resistor RT from this pin to AGND to program the switching frequency, or leave floating for the 500-kHz default. |
| 8 | PGOOD | output | Open-drain power-good flag output that requires a 10-kΩ to 100-kΩ pullup to a logic rail or DC voltage no higher than 12 V. |
| 9 | FB | input | Feedback sense input connected to the midpoint of the feedback divider to set VOUT, and must not be shorted to ground during operation. |
| 10 | AGND | power_in | Analog ground and ground reference for internal references and logic, to be connected to system ground. |
| 11 | SS/TRK | passive | Soft-start control pin: leave floating for internal soft-start slew rate, connect a capacitor to extend soft-start time, or connect an external voltage ramp for tracking. |
| 12 | EN | input | Enable input where high turns the device ON and low turns it OFF, connected to VIN, a resistor divider, or an external voltage or logic source, and must not float. |
| 13 | VIN | power_in | Supply input to the internal LDO and high-side power FET, connected to the power supply and bypass capacitor CIN with the VIN-to-CIN-to-PGND path kept as short as possible. |
| 14 | VIN | power_in | Supply input to the internal LDO and high-side power FET, connected to the power supply and bypass capacitor CIN with the VIN-to-CIN-to-PGND path kept as short as possible. |
| 15 | PGND | power_in | Power ground connected internally to the low-side power FET, to be connected to system ground, PAD, AGND, and the grounds of CIN and COUT with a short path to CIN. |
| 16 | PGND | power_in | Power ground connected internally to the low-side power FET, to be connected to system ground, PAD, AGND, and the grounds of CIN and COUT with a short path to CIN. |
| 17 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-16-EP |
| Category | Power Supply Chip |
| Pins | 17 |
CAD (KiCad official)
- Symbol:
LM46002AQPWPTQ1 - Footprint:
Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm - 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)
- 3D model files:
lm46002aqpwptq1-etched.step/lm46002aqpwptq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm46002aqpwptq1.step/lm46002aqpwptq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (51 pp, sha256
c18503df0395799f, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LM46002AQPWPTQ1
**Texas Instruments** · DC-DC Converters · HTSSOP-16-EP
LM46002AQPWPTQ1 from Texas Instruments, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | power_out | Switching output of the regulator, internally connected to both power MOSFETs, and connected to the power inductor. |
| 2 | SW | power_out | Switching output of the regulator, internally connected to both power MOSFETs, and connected to the power inductor. |
| 3 | CBOOT | power_out | Bootstrap capacitor connection for the high-side driver; connect a high-quality 470-nF capacitor from CBOOT to SW. |
| 4 | VCC | power_out | Internal bias supply output for bypassing; connect a bypass capacitor to AGND, do not connect an external load, and never short it to ground during operation. |
| 5 | BIAS | power_in | Optional internal LDO supply input: tie to VOUT when 3.3 V ≤ VOUT ≤ 28 V (or to an external 3.3-V or 5-V rail), with a 1 to 10 µF bypass capacitor to ground, and tie to ground when not used. |
| 6 | SYNC | input | Clock input to synchronize switching to an external clock, which requires proper high-speed termination to prevent ringing, and connect to ground if not used. |
| 7 | RT | passive | Connect a resistor RT from this pin to AGND to program the switching frequency, or leave floating for the 500-kHz default. |
| 8 | PGOOD | output | Open-drain power-good flag output that requires a 10-kΩ to 100-kΩ pullup to a logic rail or DC voltage no higher than 12 V. |
| 9 | FB | input | Feedback sense input connected to the midpoint of the feedback divider to set VOUT, and must not be shorted to ground during operation. |
| 10 | AGND | power_in | Analog ground and ground reference for internal references and logic, to be connected to system ground. |
| 11 | SS/TRK | passive | Soft-start control pin: leave floating for internal soft-start slew rate, connect a capacitor to extend soft-start time, or connect an external voltage ramp for tracking. |
| 12 | EN | input | Enable input where high turns the device ON and low turns it OFF, connected to VIN, a resistor divider, or an external voltage or logic source, and must not float. |
| 13 | VIN | power_in | Supply input to the internal LDO and high-side power FET, connected to the power supply and bypass capacitor CIN with the VIN-to-CIN-to-PGND path kept as short as possible. |
| 14 | VIN | power_in | Supply input to the internal LDO and high-side power FET, connected to the power supply and bypass capacitor CIN with the VIN-to-CIN-to-PGND path kept as short as possible. |
| 15 | PGND | power_in | Power ground connected internally to the low-side power FET, to be connected to system ground, PAD, AGND, and the grounds of CIN and COUT with a short path to CIN. |
| 16 | PGND | power_in | Power ground connected internally to the low-side power FET, to be connected to system ground, PAD, AGND, and the grounds of CIN and COUT with a short path to CIN. |
| 17 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-16-EP |
| Category | Power Supply Chip |
| Pins | 17 |
## CAD (KiCad official)
- Symbol: `LM46002AQPWPTQ1`
- Footprint: `Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm`
- 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)
- 3D model files: `lm46002aqpwptq1-etched.step` / `lm46002aqpwptq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lm46002aqpwptq1.step` / `lm46002aqpwptq1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lm46002-q1) (51 pp, sha256 `c18503df0395799f`, retrieved 2026-10-08, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/lm46002aqpwptq1-datasheet.pdf)