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LM46002AQPWPTQ1
Public Made by Adomby adom
Texas Instruments DC-DC Converters, HTSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+54@@ -0,0 +1,54 @@+# LM46002AQPWPTQ1++**Texas Instruments** · DC-DC Converters · HTSSOP-16-EP++LM46002AQPWPTQ1 from Texas Instruments, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | SW | power_out | Switching output of the regulator, internally connected to both power MOSFETs, and connected to the power inductor. |+| 2 | SW | power_out | Switching output of the regulator, internally connected to both power MOSFETs, and connected to the power inductor. |+| 3 | CBOOT | power_out | Bootstrap capacitor connection for the high-side driver; connect a high-quality 470-nF capacitor from CBOOT to SW. |+| 4 | VCC | power_out | Internal bias supply output for bypassing; connect a bypass capacitor to AGND, do not connect an external load, and never short it to ground during operation. |+| 5 | BIAS | power_in | Optional internal LDO supply input: tie to VOUT when 3.3 V ≤ VOUT ≤ 28 V (or to an external 3.3-V or 5-V rail), with a 1 to 10 µF bypass capacitor to ground, and tie to ground when not used. |+| 6 | SYNC | input | Clock input to synchronize switching to an external clock, which requires proper high-speed termination to prevent ringing, and connect to ground if not used. |+| 7 | RT | passive | Connect a resistor RT from this pin to AGND to program the switching frequency, or leave floating for the 500-kHz default. |+| 8 | PGOOD | output | Open-drain power-good flag output that requires a 10-kΩ to 100-kΩ pullup to a logic rail or DC voltage no higher than 12 V. |+| 9 | FB | input | Feedback sense input connected to the midpoint of the feedback divider to set VOUT, and must not be shorted to ground during operation. |+| 10 | AGND | power_in | Analog ground and ground reference for internal references and logic, to be connected to system ground. |+| 11 | SS/TRK | passive | Soft-start control pin: leave floating for internal soft-start slew rate, connect a capacitor to extend soft-start time, or connect an external voltage ramp for tracking. |+| 12 | EN | input | Enable input where high turns the device ON and low turns it OFF, connected to VIN, a resistor divider, or an external voltage or logic source, and must not float. |+| 13 | VIN | power_in | Supply input to the internal LDO and high-side power FET, connected to the power supply and bypass capacitor CIN with the VIN-to-CIN-to-PGND path kept as short as possible. |+| 14 | VIN | power_in | Supply input to the internal LDO and high-side power FET, connected to the power supply and bypass capacitor CIN with the VIN-to-CIN-to-PGND path kept as short as possible. |+| 15 | PGND | power_in | Power ground connected internally to the low-side power FET, to be connected to system ground, PAD, AGND, and the grounds of CIN and COUT with a short path to CIN. |+| 16 | PGND | power_in | Power ground connected internally to the low-side power FET, to be connected to system ground, PAD, AGND, and the grounds of CIN and COUT with a short path to CIN. |+| 17 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | HTSSOP-16-EP |+| Category | Power Supply Chip |+| Pins | 17 |++## CAD (KiCad official)++- Symbol: `LM46002AQPWPTQ1`+- Footprint: `Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm`+- 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)+- 3D model files: `lm46002aqpwptq1-etched.step` / `lm46002aqpwptq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lm46002aqpwptq1.step` / `lm46002aqpwptq1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lm46002-q1) (51 pp, sha256 `c18503df0395799f`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/lm46002aqpwptq1-datasheet.pdf)
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connect a high-quality 470-nF capacitor from CBOOT to SW."+ },+ {+ "number": "4",+ "name": "VCC",+ "type": "power_out",+ "description": "Internal bias supply output for bypassing; connect a bypass capacitor to AGND, do not connect an external load, and never short it to ground during operation."+ },+ {+ "number": "5",+ "name": "BIAS",+ "type": "power_in",+ "description": "Optional internal LDO supply input: tie to VOUT when 3.3 V ≤ VOUT ≤ 28 V (or to an external 3.3-V or 5-V rail), with a 1 to 10 µF bypass capacitor to ground, and tie to ground when not used."+ },+ {+ "number": "6",+ "name": "SYNC",+ "type": "input",+ "description": "Clock input to synchronize switching to an external clock, which requires proper high-speed termination to prevent ringing, and connect to ground if not used."+ },+ {+ "number": "7",+ "name": "RT",+ "type": "passive",+ "description": "Connect a resistor RT from this pin to AGND to program the switching frequency, or leave floating for the 500-kHz default."+ },+ {+ "number": "8",+ "name": "PGOOD",+ "type": "output",+ "description": "Open-drain power-good flag output that requires a 10-kΩ to 100-kΩ pullup to a logic rail or DC voltage no higher than 12 V."+ },+ {+ "number": "9",+ "name": "FB",+ "type": "input",+ "description": "Feedback sense input connected to the midpoint of the feedback divider to set VOUT, and must not be shorted to ground during operation."+ },+ {+ "number": "10",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground and ground reference for internal references and logic, to be connected to system ground."+ },+ {+ "number": "11",+ "name": "SS/TRK",+ "type": "passive",+ "description": "Soft-start control pin: leave floating for internal soft-start slew rate, connect a capacitor to extend soft-start time, or connect an external voltage ramp for tracking."+ },+ {+ "number": "12",+ "name": "EN",+ "type": "input",+ "description": "Enable input where high turns the device ON and low turns it OFF, connected to VIN, a resistor divider, or an external voltage or logic source, and must not float."+ },+ {+ "number": "13",+ "name": "VIN",+ "type": "power_in",+ "description": "Supply input to the internal LDO and high-side power FET, connected to the power supply and bypass capacitor CIN with the VIN-to-CIN-to-PGND path kept as short as possible."+ },+ {+ "number": "14",+ "name": "VIN",+ "type": "power_in",+ "description": "Supply input to the internal LDO and high-side power FET, connected to the power supply and bypass capacitor CIN with the VIN-to-CIN-to-PGND path kept as short as possible."+ },+ {+ "number": "15",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground connected internally to the low-side power FET, to be connected to system ground, PAD, AGND, and the grounds of CIN and COUT with a short path to CIN."+ },+ {+ "number": "16",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground connected internally to the low-side power FET, to be connected to system ground, PAD, AGND, and the grounds of CIN and COUT with a short path to CIN."+ },+ {+ "number": "17",+ "name": "PAD",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The exposed thermal pad is listed in the datasheet pin table (page 3) with no printed pin number, so; Pin types are KiCad ERC classes mapped from the datasheet's P/G/A/I-O column; SW, CBOOT and VCC are ",+ "exposed pad 17 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 7,+ "cost_usd": 0.058,+ "at": "2026-10-08T20:45:57"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/lm46002-q1",+ "pages": 51,+ "sha256": "c18503df0395799f",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 17,+ "described": 17,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "lm46002aqpwptq1.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "7982746831c0bd23f4690608869ad67776faae5c762fb0376666126a3998921b",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "lm46002aqpwptq1-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "4d21b4b4130d7b2c8f86392ce3ec0fe2b03da842354e4365c66fdb83eedbbde9",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}