# LM43601AQPWPRQ1

**Texas Instruments** · DC-DC Converters · HTSSOP-16-EP

LM43601AQPWPRQ1 from Texas Instruments, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | power_out | Switching output of the regulator, internally connected to both power MOSFETs, to be connected to the power inductor. |
| 2 | SW | power_out | Switching output of the regulator, internally connected to both power MOSFETs, to be connected to the power inductor. |
| 3 | CBOOT | passive | Bootstrap capacitor connection for the high-side driver, where a high-quality 470-nF capacitor is connected from CBOOT to SW. |
| 4 | VCC | power_out | Internal bias supply output for bypassing, with a bypass capacitor connected from this pin to AGND; no external load may be connected and the pin must never be shorted to ground during operation. |
| 5 | BIAS | power_in | Optional internal LDO supply input, recommended tied to VOUT for 3.3 V ≤ VOUT ≤ 28 V or to an external 3.3-V or 5-V rail, with a 1 to 10 µF bypass to ground, and tied to ground when not used. |
| 6 | SYNC | input | Clock input that synchronizes switching to an external clock, requiring proper high-speed termination to prevent ringing, and it must be connected to ground if not used and not left floating. |
| 7 | RT | passive | Resistor RT connected from this pin to AGND programs the switching frequency, and the pin is left floating for the 500 kHz default. |
| 8 | PGOOD | output | Open-drain power-good flag output that requires a 10-kΩ to 100-kΩ pullup to a logic rail or DC voltage no higher than 12 V. |
| 9 | FB | input | Feedback sense input connected to the midpoint of the feedback divider to set VOUT, and must not be shorted to ground during operation. |
| 10 | AGND | power_in | Analog ground pin serving as ground reference for internal references and logic, to be connected to system ground. |
| 11 | SS/TRK | input | Soft-start control pin that is left floating for the internal soft-start slew rate, connected to a capacitor to extend soft-start time, or connected to an external voltage ramp for tracking. |
| 12 | EN | input | Enable input where high turns the device ON and low turns it OFF, connected to VIN, a resistor divider, or an external voltage or logic source, and must not be left floating. |
| 13 | VIN | power_in | Supply input pin to the internal LDO and high-side power FET, requiring bypass capacitors CIN with the VIN-to-CIN-to-PGND path kept as short as possible. |
| 14 | VIN | power_in | Supply input pin to the internal LDO and high-side power FET, requiring bypass capacitors CIN with the VIN-to-CIN-to-PGND path kept as short as possible. |
| 15 | PGND | power_in | Power ground pin connected internally to the low-side power FET, to be connected to system ground, PAD, AGND, and the ground pins of CIN and COUT with a short path to CIN. |
| 16 | PGND | power_in | Power ground pin connected internally to the low-side power FET, to be connected to system ground, PAD, AGND, and the ground pins of CIN and COUT with a short path to CIN. |
| 17 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-16-EP |
| Category | Power Supply Chip |
| Pins | 17 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN to PGND |  | -0.3 |  | 42 | V |  | 4 |
| EN to PGND |  | -0.3 |  |  | V |  | 4 |
| FB, RT, SS/TRK to AGND |  | -0.3 |  | 3.6 | V |  | 4 |
| PGOOD to AGND |  | -0.3 |  | 15 | V |  | 4 |
| SYNC to AGND |  | -0.3 |  | 5.5 | V |  | 4 |
| BIAS to AGND |  | -0.3 |  | 30 | V |  | 4 |
| AGND to PGND |  | -0.3 |  | 0.3 | V |  | 4 |
| SW to PGND |  | -0.3 |  |  | V |  | 4 |
| SW to PGND less than 10-ns transients |  | -3.5 |  | 42 | V |  | 4 |
| CBOOT to SW |  | -0.3 |  | 5.5 | V |  | 4 |
| VCC to AGND |  | -0.3 |  | 3.6 | V |  | 4 |
| Storage temperature range | Tstg | -65 |  | 150 | °C |  | 4 |
| VIN to PGND |  | 3.5 |  | 36 | V |  | 4 |
| EN |  | -0.3 |  |  | V |  | 4 |
| FB |  | -0.3 |  | 1.1 | V |  | 4 |
| PGOOD |  | -0.3 |  | 12 | V |  | 4 |
| BIAS input not used |  | -0.3 |  | 0.3 | V |  | 4 |
| BIAS input used |  | 3.3 |  |  | V |  | 4 |
| AGND to PGND |  | -0.1 |  | 0.1 | V |  | 4 |
| Output voltage | VOUT | 1 |  | 28 | V |  | 4 |
| Output current | IOUT | 0 |  | 1 | A |  | 4 |
| Operating junction temperature range | TJ | -40 |  | 125 | °C |  | 4 |
| Minimum input voltage for start-up | VIN-MIN-ST | 3.8 |  |  | V |  | 5 |
| Shutdown quiescent current | ISHDN |  | 1.1 | 3.1 | µA | VEN = 0 V | 5 |
| Operating quiescent current (non-switching) from VIN | IQ-NONSW |  | 6 | 11 | µA | VEN = 3.3 V, VFB = 1.5 V, VBIAS = 3.4 V external | 5 |
| Operating quiescent current (non-switching) from external VBIAS | IBIAS-NONSW |  | 85 | 140 | µA | VEN = 3.3 V, VFB = 1.5 V, VBIAS = 3.4 V external | 5 |
| Precision enable level for switching and regulator output: VOUT | VEN-VOUT-H | 2 | 2.1 | 2.42 | V | VENABLE high level | 5 |
| Enable input leakage current | ILKG-EN |  | 0.8 | 1.75 | µA | VEN = 3.3 V | 5 |
| Internal LDO input change over threshold to BIAS | VBIAS-ON |  | 2.96 | 3.2 | V | VBIAS rising threshold | 5 |
| Feedback voltage, TJ = 25ºC | VFB | 1.009 | 1.016 | 1.023 | V | TJ = 25ºC | 6 |
| Feedback voltage, TJ = -40ºC to 125ºC | VFB | 0.999 | 1.016 | 1.039 | V | TJ = -40ºC to 125ºC | 6 |
| Input leakage current at FB pin | ILKG-FB |  | 0.2 | 65 | nA | FB = 1.016 V | 6 |
| Peak inductor current limit | IHS-LIMIT | 2.07 | 2.45 | 2.71 | A |  | 6 |
| Valley inductor current limit | ILS-LIMIT | 0.94 | 1.1 | 1.25 | A |  | 6 |
| Soft-start charge current | ISSC | 1.17 | 2.2 | 2.85 | µA |  | 6 |
| Power-good flag overvoltage tripping threshold | VPGOOD-HIGH |  | 110 | 113 | % | % of FB voltage | 6 |
| Power-good flag undervoltage tripping threshold | VPGOOD-LOW |  | 83 | 90 | % | % of FB voltage | 6 |
| PGOOD pin pulldown resistance when power bad (LM43601A-Q1) | RPGOOD |  | 69 | 150 | Ω | LM43601A-Q1: VEN = 3.3 V | 6 |
| PGOOD pin pulldown resistance when power bad (LM43601A-Q1) | RPGOOD |  | 150 | 350 | Ω | LM43601A-Q1: VEN = 0 V | 6 |
| Minimum high side MOSFET ON-time | TON-MIN |  | 125 | 165 | ns |  | 7 |
| Minimum high side MOSFET OFF-time | TOFF-MIN |  | 200 | 250 | ns |  | 7 |
| Oscillator default frequency | FOSC-DEFAULT | 445 | 500 | 570 | kHz | RT pin open circuit | 7 |
| Minimum adjustable frequency | FADJ | 200 |  |  | kHz | With 1% resistors at RT pin | 7 |
| Maximum adjustable frequency |  |  |  | 2200 | kHz |  | 7 |
| Frequency adjust accuracy |  | -10 |  | 10 | % |  | 7 |
| Sync clock high level threshold | VSYNC-HIGH | 2 |  |  | V |  | 7 |
| Sync clock low level threshold | VSYNC-LOW |  |  | 0.4 | V |  | 7 |
| Sync clock maximum duty cycle | DSYNC-MAX |  |  | 90 | % |  | 7 |
| Sync clock minimum duty cycle | DSYNC-MIN | 10 |  |  | % |  | 7 |
| Minimum sync clock ON- and OFF-time | TSYNC-MIN | 80 |  |  | ns |  | 7 |
| Internal LDO output voltage VCC | VCC |  | 3.3 |  | V | VIN ≥ 3.8 V | 5 |
| Voltage level to enable the internal LDO output VCC | VEN-VCC-H |  | 1.2 |  | V | VENABLE high level | 5 |
| Operating quiescent current (switching) | IQ-SW |  | 33 |  | µA | VEN = 3.3 V; IOUT = 0 A; RT = open; VBIAS = VOUT = 3.3 V; RFBT = 1 Meg | 5 |
| Thermal shutdown threshold | TSD |  | 160 |  | ºC | Shutdown threshold | 6 |
| High-side MOSFET ON-resistance | RDS-ON-HS |  | 419 |  | mΩ | IOUT = 1 A; VBIAS = VOUT = 3.3 V | 6 |
| Low-side MOSFET ON-resistance | RDS-ON-LS |  | 231 |  | mΩ | IOUT = 1 A; VBIAS = VOUT = 3.3 V | 6 |
| Junction-to-ambient thermal resistance | RθJA |  | 39.9 |  | °C/W | JESD 51-7, 4-layer board, 1 W power dissipation | 5 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 26.9 |  | °C/W |  | 5 |
| Junction-to-board thermal resistance | RθJB |  | 21.7 |  | °C/W |  | 5 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) |  | 2.3 |  | °C/W |  | 5 |

## CAD (KiCad official)

- Symbol: `LM43601AQPWPRQ1`
- Footprint: `Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm`
- 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)
- 3D model files: `lm43601aqpwprq1-etched.step` / `lm43601aqpwprq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lm43601aqpwprq1.step` / `lm43601aqpwprq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lm43601-q1) (51 pp, sha256 `b035d735bd2ad002`, retrieved 2026-10-12, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lm43601aqpwprq1-datasheet.pdf)