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LM25119PSQX
Public Made by Adomby adom
Texas Instruments DC-DC Converters, WQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LM25119PSQX
Texas Instruments · DC-DC Converters · WQFN-32-EP(5x5)
LM25119PSQX from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC1 | power_out | Channel 1 VCC bias pin; limits are -0.3 V to 15 V to AGND (recommended 4.5 V to 14 V), and it must not exceed VIN. |
| 2 | LO1 | output | Channel 1 low-side MOSFET gate drive output, to be connected to the synchronous MOSFET gate through a short, low-inductance path; LO1 to AGND is limited to -0.3 V to VVCC + 0.3 V. |
| 3 | PGND1 | power_in | Power ground return for the channel 1 low-side MOSFET gate driver, to be connected directly to the low side of the channel 1 current sense resistor. |
| 4 | CSG1 | input | Kelvin ground connection for the channel 1 external current sense resistor, to be connected directly to its low side. |
| 5 | CS1 | input | Channel 1 current sense amplifier input, to be connected to the high side of the channel 1 current sense resistor; CS1 to AGND is limited to -0.3 V to 0.3 V. |
| 6 | RAMP1 | input | Channel 1 PWM ramp signal; an external RC network between SW1, RAMP1 and AGND sets the emulated inductor-current ramp slope. |
| 7 | SS1 | input | Channel 1 soft-start pin; an external capacitor with an internal 10-µA source sets the error amplifier reference ramp rate, and SS1 is held low when VCC1 or VCC2 is below 4 V, UVLO is below 1.25 V, or during thermal shutdown. |
| 8 | VCCDIS | input | Optional input that disables the internal VCC regulators when VCCDIS is above 1.25 V for external bias; it has a 500-kΩ pulldown to ground. |
| 9 | FB1 | input | Channel 1 feedback input and inverting input of the internal error amplifier, with a regulation threshold of 0.8 V. |
| 10 | COMP1 | output | Channel 1 internal error amplifier output; the loop compensation network must be connected between this pin and FB1. |
| 11 | EN2 | input | Channel 2 enable; when low, channel 2 is disabled while channel 1 and other functions remain active, and the pin has an internal 50-kΩ pullup. |
| 12 | AGND | power_in | Analog ground, the return for the internal 0.8-V voltage reference and analog circuits. |
| 13 | RT | input | Oscillator timing pin set by a single resistor to AGND; the recommended maximum oscillator frequency is 1.5 MHz, corresponding to a 750-kHz maximum switching frequency per channel, and it can be synchronized by a positive pulse coupled through a small capacitor. |
| 14 | RES | output | Restart timer pin for an external capacitor that sets the hiccup-mode off time; a 10-µA source charges it to the 1.25-V restart threshold after 256 consecutive cycle-by-cycle current-limit PWM cycles. |
| 15 | COMP2 | output | Channel 2 internal error amplifier output; the loop compensation network must be connected between this pin and FB2. |
| 16 | FB2 | input | Channel 2 feedback input and inverting input of the internal error amplifier, with a regulation threshold of 0.8 V. |
| 17 | DEMB | input | Logic input that enables diode emulation when low and disables it when high; a 50-kΩ internal pulldown enables diode emulation if the pin is left floating. |
| 18 | SS2 | input | Channel 2 soft-start pin; an external capacitor with an internal 10-µA source sets the error amplifier reference ramp rate, and SS2 is held low when VCC1 or VCC2 is below 4 V, UVLO is below 1.25 V, or during thermal shutdown. |
| 19 | RAMP2 | input | Channel 2 PWM ramp signal; an external RC network between SW2, RAMP2 and AGND sets the emulated inductor-current ramp slope. |
| 20 | CS2 | input | Channel 2 current sense amplifier input, to be connected to the high side of the channel 2 current sense resistor; CS2 to AGND is limited to -0.3 V to 0.3 V. |
| 21 | CSG2 | input | Kelvin ground connection for the channel 2 external current sense resistor, to be connected directly to its low side. |
| 22 | PGND2 | power_in | Power ground return for the channel 2 low-side MOSFET gate driver, to be connected directly to the low side of the channel 2 current sense resistor. |
| 23 | LO2 | output | Channel 2 low-side MOSFET gate drive output, to be connected to the synchronous MOSFET gate through a short, low-inductance path; LO2 to AGND is limited to -0.3 V to VVCC + 0.3 V. |
| 24 | VCC2 | power_out | Channel 2 VCC bias pin; limits are -0.3 V to 15 V to AGND (recommended 4.5 V to 14 V), and it must not exceed VIN. |
| 25 | SW2 | bidirectional | Channel 2 buck switching node, connected to the channel 2 bootstrap capacitor, the high-side MOSFET source and the low-side MOSFET drain; SW2 to AGND is limited to -3 V to 45 V. |
| 26 | HO2 | output | Channel 2 high-side MOSFET gate drive output, to be connected to the gate of the high-side MOSFET through a short, low-inductance path; HO2 to SW2 is limited to -0.3 V to VHB + 0.3 V. |
| 27 | HB2 | power_in | Channel 2 high-side driver bootstrap supply, connected to the bootstrap diode cathode and bootstrap capacitor, which must be placed as close to the controller as possible; HB to SW is limited to 4.5 V to 14 V. |
| 28 | UVLO | input | Undervoltage lockout programming pin; below 0.4 V the regulator shuts down, between 0.4 V and 1.25 V it is in standby with no switching, and above 1.25 V switching is enabled, with a 20-µA hysteresis current source. |
| 29 | VIN | power_in | Supply voltage input for the VCC regulators; the recommended range is 4.5 V to 42 V and the absolute maximum is 45 V to AGND. |
| 30 | HB1 | power_in | Channel 1 high-side driver bootstrap supply, connected to the bootstrap diode cathode and bootstrap capacitor, which must be placed as close to the controller as possible; HB to SW is limited to 4.5 V to 14 V. |
| 31 | HO1 | output | Channel 1 high-side MOSFET gate drive output, to be connected to the gate of the high-side MOSFET through a short, low-inductance path; HO1 to SW1 is limited to -0.3 V to VHB + 0.3 V. |
| 32 | SW1 | bidirectional | Channel 1 buck switching node, connected to the channel 1 bootstrap capacitor, the high-side MOSFET source and the low-side MOSFET drain; SW1 to AGND is limited to -3 V to 45 V. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-32-EP(5x5) |
| Category | Power Management (PMIC) |
| Pins | 33 |
CAD (KiCad official)
- Symbol:
LM25119PSQX - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
lm25119psqx-etched.step/lm25119psqx-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm25119psqx.step/lm25119psqx.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (45 pp, sha256
ce7cb7dea581ea97, retrieved 2026-10-10, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LM25119PSQX
**Texas Instruments** · DC-DC Converters · WQFN-32-EP(5x5)
LM25119PSQX from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC1 | power_out | Channel 1 VCC bias pin; limits are -0.3 V to 15 V to AGND (recommended 4.5 V to 14 V), and it must not exceed VIN. |
| 2 | LO1 | output | Channel 1 low-side MOSFET gate drive output, to be connected to the synchronous MOSFET gate through a short, low-inductance path; LO1 to AGND is limited to -0.3 V to VVCC + 0.3 V. |
| 3 | PGND1 | power_in | Power ground return for the channel 1 low-side MOSFET gate driver, to be connected directly to the low side of the channel 1 current sense resistor. |
| 4 | CSG1 | input | Kelvin ground connection for the channel 1 external current sense resistor, to be connected directly to its low side. |
| 5 | CS1 | input | Channel 1 current sense amplifier input, to be connected to the high side of the channel 1 current sense resistor; CS1 to AGND is limited to -0.3 V to 0.3 V. |
| 6 | RAMP1 | input | Channel 1 PWM ramp signal; an external RC network between SW1, RAMP1 and AGND sets the emulated inductor-current ramp slope. |
| 7 | SS1 | input | Channel 1 soft-start pin; an external capacitor with an internal 10-µA source sets the error amplifier reference ramp rate, and SS1 is held low when VCC1 or VCC2 is below 4 V, UVLO is below 1.25 V, or during thermal shutdown. |
| 8 | VCCDIS | input | Optional input that disables the internal VCC regulators when VCCDIS is above 1.25 V for external bias; it has a 500-kΩ pulldown to ground. |
| 9 | FB1 | input | Channel 1 feedback input and inverting input of the internal error amplifier, with a regulation threshold of 0.8 V. |
| 10 | COMP1 | output | Channel 1 internal error amplifier output; the loop compensation network must be connected between this pin and FB1. |
| 11 | EN2 | input | Channel 2 enable; when low, channel 2 is disabled while channel 1 and other functions remain active, and the pin has an internal 50-kΩ pullup. |
| 12 | AGND | power_in | Analog ground, the return for the internal 0.8-V voltage reference and analog circuits. |
| 13 | RT | input | Oscillator timing pin set by a single resistor to AGND; the recommended maximum oscillator frequency is 1.5 MHz, corresponding to a 750-kHz maximum switching frequency per channel, and it can be synchronized by a positive pulse coupled through a small capacitor. |
| 14 | RES | output | Restart timer pin for an external capacitor that sets the hiccup-mode off time; a 10-µA source charges it to the 1.25-V restart threshold after 256 consecutive cycle-by-cycle current-limit PWM cycles. |
| 15 | COMP2 | output | Channel 2 internal error amplifier output; the loop compensation network must be connected between this pin and FB2. |
| 16 | FB2 | input | Channel 2 feedback input and inverting input of the internal error amplifier, with a regulation threshold of 0.8 V. |
| 17 | DEMB | input | Logic input that enables diode emulation when low and disables it when high; a 50-kΩ internal pulldown enables diode emulation if the pin is left floating. |
| 18 | SS2 | input | Channel 2 soft-start pin; an external capacitor with an internal 10-µA source sets the error amplifier reference ramp rate, and SS2 is held low when VCC1 or VCC2 is below 4 V, UVLO is below 1.25 V, or during thermal shutdown. |
| 19 | RAMP2 | input | Channel 2 PWM ramp signal; an external RC network between SW2, RAMP2 and AGND sets the emulated inductor-current ramp slope. |
| 20 | CS2 | input | Channel 2 current sense amplifier input, to be connected to the high side of the channel 2 current sense resistor; CS2 to AGND is limited to -0.3 V to 0.3 V. |
| 21 | CSG2 | input | Kelvin ground connection for the channel 2 external current sense resistor, to be connected directly to its low side. |
| 22 | PGND2 | power_in | Power ground return for the channel 2 low-side MOSFET gate driver, to be connected directly to the low side of the channel 2 current sense resistor. |
| 23 | LO2 | output | Channel 2 low-side MOSFET gate drive output, to be connected to the synchronous MOSFET gate through a short, low-inductance path; LO2 to AGND is limited to -0.3 V to VVCC + 0.3 V. |
| 24 | VCC2 | power_out | Channel 2 VCC bias pin; limits are -0.3 V to 15 V to AGND (recommended 4.5 V to 14 V), and it must not exceed VIN. |
| 25 | SW2 | bidirectional | Channel 2 buck switching node, connected to the channel 2 bootstrap capacitor, the high-side MOSFET source and the low-side MOSFET drain; SW2 to AGND is limited to -3 V to 45 V. |
| 26 | HO2 | output | Channel 2 high-side MOSFET gate drive output, to be connected to the gate of the high-side MOSFET through a short, low-inductance path; HO2 to SW2 is limited to -0.3 V to VHB + 0.3 V. |
| 27 | HB2 | power_in | Channel 2 high-side driver bootstrap supply, connected to the bootstrap diode cathode and bootstrap capacitor, which must be placed as close to the controller as possible; HB to SW is limited to 4.5 V to 14 V. |
| 28 | UVLO | input | Undervoltage lockout programming pin; below 0.4 V the regulator shuts down, between 0.4 V and 1.25 V it is in standby with no switching, and above 1.25 V switching is enabled, with a 20-µA hysteresis current source. |
| 29 | VIN | power_in | Supply voltage input for the VCC regulators; the recommended range is 4.5 V to 42 V and the absolute maximum is 45 V to AGND. |
| 30 | HB1 | power_in | Channel 1 high-side driver bootstrap supply, connected to the bootstrap diode cathode and bootstrap capacitor, which must be placed as close to the controller as possible; HB to SW is limited to 4.5 V to 14 V. |
| 31 | HO1 | output | Channel 1 high-side MOSFET gate drive output, to be connected to the gate of the high-side MOSFET through a short, low-inductance path; HO1 to SW1 is limited to -0.3 V to VHB + 0.3 V. |
| 32 | SW1 | bidirectional | Channel 1 buck switching node, connected to the channel 1 bootstrap capacitor, the high-side MOSFET source and the low-side MOSFET drain; SW1 to AGND is limited to -3 V to 45 V. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-32-EP(5x5) |
| Category | Power Management (PMIC) |
| Pins | 33 |
## CAD (KiCad official)
- Symbol: `LM25119PSQX`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`
- 3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `lm25119psqx-etched.step` / `lm25119psqx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lm25119psqx.step` / `lm25119psqx.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lm25119) (45 pp, sha256 `ce7cb7dea581ea97`, retrieved 2026-10-10, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/lm25119psqx-datasheet.pdf)