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Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
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lm21215mhx-etched.glb	lm21215mhx: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	17d ago
lm21215mhx-etched.step	lm21215mhx: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	17d ago
lm21215mhx-hero.glb	lm21215mhx: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	17d ago
lm21215mhx-hero.overlay.json	lm21215mhx: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	17d ago
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lm21215mhx.kicad_sym	Publish 0.1.0 · Ray	21d ago
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lm21215mhx.step	plain STEP: one free product with face colours (generated model was nested; tscircuit read it white) · Ray	17d ago
package.json	lm21215mhx: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	17d ago
page.json	lm21215mhx: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	17d ago
README.md	Publish 0.1.0 · Ray	21d ago

LM21215MHX

Texas Instruments · DC-DC Converters · HTSSOP-20-EP

LM21215MHX from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	ILIM	passive	Resistor-programmable current limit pin; a resistor to ground sets the rising current limit ICLR, and shorting this pin to AGND selects the maximum possible current limit.
2	SS/TRK	passive	Soft-start control pin; an internal 2 µA current source charges an external capacitor to AGND to set the start-up output ramp rate, and the pin also configures the tracking feature.
3	EN	input	Active-high enable input for the device; if not used it can be left open, as an internal current source pulls it high.
4	AVIN	power_in	Analog input supply that generates the internal bias, recommended to connect to PVIN through a low-pass RC filter; recommended range is 2.95 V to 5.5 V to GND.
5	PVIN	power_in	Input voltage to the internal power switches, to be tied together with pins 6 and 7 at the device with low-ESR input capacitance placed as close as possible; recommended range is 2.95 V to 5.5 V to GND.
6	PVIN	power_in	Input voltage to the internal power switches, to be tied together with pins 5 and 7 at the device with low-ESR input capacitance placed as close as possible; recommended range is 2.95 V to 5.5 V to GND.
7	PVIN	power_in	Input voltage to the internal power switches, to be tied together with pins 5 and 6 at the device with low-ESR input capacitance placed as close as possible; recommended range is 2.95 V to 5.5 V to GND.
8	PGND	power_in	Power ground pin for the internal power switches, to be grouped with pins 9 and 10.
9	PGND	power_in	Power ground pin for the internal power switches, to be grouped with pins 8 and 10.
10	PGND	power_in	Power ground pin for the internal power switches, to be grouped with pins 8 and 9.
11	SW	output	Switch node pin, to be tied together locally with pins 12-16 and connected to the filter inductor.
12	SW	output	Switch node pin, to be tied together locally with pins 11 and 13-16 and connected to the filter inductor.
13	SW	output	Switch node pin, to be tied together locally with pins 11-12 and 14-16 and connected to the filter inductor.
14	SW	output	Switch node pin, to be tied together locally with pins 11-13 and 15-16 and connected to the filter inductor.
15	SW	output	Switch node pin, to be tied together locally with pins 11-14 and 16 and connected to the filter inductor.
16	SW	output	Switch node pin, to be tied together locally with pins 11-15 and connected to the filter inductor.
17	PGOOD	output	Open-drain power good indicator output.
18	COMP	passive	Compensation pin connected to the output of the voltage loop error amplifier.
19	FB	input	Feedback pin connected to the inverting input of the voltage loop error amplifier; the feedback reference is 0.6 V (±1%).
20	AGND	power_in	Quiet analog ground for the internal reference and bias circuitry.
21	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	HTSSOP-20-EP
Category	Power Management (PMIC)
Pins	21

CAD (KiCad official)

Symbol: LM21215MHX
Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: lm21215mhx-etched.step / lm21215mhx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm21215mhx.step / lm21215mhx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (40 pp, sha256 08d986dd316137de, retrieved 2026-10-12, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF