# LGE2310

**LGE** · MOSFETs · SOT-23

LGE2310 from LGE, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate; gate-source voltage limited to ±20 V, threshold VGS(th) 0.5 V min to 2 V max at ID=250µA. |
| 2 | S | passive | Source; continuous drain current 3 A and pulsed drain current 10 A rating (note 1). |
| 3 | D | passive | Drain; drain-source voltage rated 60 V, RDS(on) below 105 mΩ at VGS=10V and below 125 mΩ at VGS=4.5V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | LGE |
| Package | SOT-23 |
| Category | Transistors/Thyristors |
| Pins | 3 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS |  |  | 60 | V |  | 1 |
| Gate-Source Voltage | VGS | -20 |  | 20 | V |  | 1 |
| Continuous Drain Current | ID |  |  | 3 | A |  | 1 |
| Pulsed Drain Current | IDM |  |  | 10 | A | Repetitive rating; pulse width limited by maximum junction temperature (note 1) | 1 |
| Maximum Power Dissipation | PD |  |  | 0.35 | W |  | 1 |
| Thermal Resistance from Junction to Ambient | RθJA |  |  | 357 | ℃/W | Surface mounted on FR4 board, t≤10 sec (note 2) | 1 |
| Junction and Storage Temperature | TJ、TSTG | -55 |  | 150 | ℃ |  | 1 |
| Drain-source breakdown voltage | V(BR)DSS | 60 |  |  | V | VGS = 0V, ID =250µA | 1 |
| Zero gate voltage drain current | IDSS |  |  | 1 | µA | VDS =60V,VGS = 0V | 1 |
| Gate-body leakage current | IGSS | -100 |  | 100 | nA | VGS =±20V, VDS = 0V | 1 |
| Gate threshold voltage (note 3) | VGS(th) | 0.5 |  | 2 | V | VDS =VGS, ID =250µA | 1 |
| Drain-source on-resistance (note 3) | RDS(on) |  |  | 105 | mΩ | VGS =10V, ID =3A | 1 |
| Drain-source on-resistance (note 3) | RDS(on) |  |  | 125 | mΩ | VGS =4.5V, ID =3A | 1 |
| Forward transconductance (note 3) | gFS |  | 1.4 |  | S | VDS =15V, ID =2A | 1 |
| Diode forward voltage (note 3) | VSD |  | 1.2 |  | V | IS=3A, VGS = 0V | 1 |
| Input Capacitance | Ciss |  | 247 |  | pF | VDS=30V,VGS=0V,f =1MHz | 2 |
| Output Capacitance | Coss |  | 34 |  | pF |  | 2 |
| Reverse Transfer Capacitance | Crss |  | 19.5 |  | pF |  | 2 |
| Turn-on delay time | td(on) |  | 6 |  | ns | VDS= 30 V,ID=1.5A, VGS=10V, RGEN =1 Ω | 2 |
| Turn-on rise time | tr |  | 15 |  | ns |  | 2 |
| Turn-off delay time | td(off) |  | 15 |  | ns |  | 2 |
| Turn-off fall time | tf |  | 10 |  | ns |  | 2 |
| Total Gate Charge | Qg |  | 6 |  | nC | VDS =30V, VGS = 4.5 V, ID = 3A | 2 |
| Gate-Source Charge | Qgs |  | 1 |  | nC |  | 2 |
| Gate-Drain Charge | Qgd |  | 1.3 |  | nC |  | 2 |

## CAD (KiCad official)

- Symbol: `LGE2310`
- Footprint: `Package_TO_SOT_SMD:SOT-23`
- 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files: `lge2310-etched.step` / `lge2310-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lge2310.step` / `lge2310.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [LGE datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603384314838982656) (4 pp, sha256 `a22e251f0df3aa40`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lge2310-datasheet.pdf)