LE87271EQCT from Microchip Tech, in a QFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NC	unconnected	No connect, no internal connection.
2	NC	unconnected	No connect, no internal connection.
3	C0	input	Tri-state logic-level state control input with an internal resistor pulling to the middle level when undriven (VIH 2.0 V min, VIL 0.8 V max, VIM 1.4 to 1.6 V on C0).
4	C1	input	Logic-level state control input with an internal pull-down resistor (VIH 2.0 V min, VIL 0.8 V max).
5	C2	input	Logic-level state control input with an internal pull-down resistor (VIH 2.0 V min, VIL 0.8 V max).
6	NC	unconnected	No connect, no internal connection.
7	IREF	passive	Bias current reference pin, connected through RREF (75 kΩ typical) to ground.
8	VDD	power_in	Power supply pin, 12.6 V to 15.4 V (14 V typical), tied together with VDD_P and VDD_N.
9	VDD_N	power_in	Power supply pin for the N output side, 12.6 V to 15.4 V (14 V typical), tied together with VDD and VDD_P.
10	NC	unconnected	No connect, no internal connection.
11	OUT_N	output	Line driver differential output (negative), high impedance in power-down and thermal shut-down.
12	NC	unconnected	No connect, no internal connection.
13	VSS	power_in	Ground pin.
14	NC	unconnected	No connect, no internal connection.
15	OUT_P	output	Line driver differential output (positive), high impedance in power-down and thermal shut-down.
16	NC	unconnected	No connect, no internal connection.
17	VDD_P	power_in	Power supply pin for the P output side, 12.6 V to 15.4 V (14 V typical), tied together with VDD and VDD_N.
18	VDD	power_in	Power supply pin, 12.6 V to 15.4 V (14 V typical), tied together with VDD_P and VDD_N.
19	IN_P	input	Line driver differential input (positive), 15 kΩ typical differential input impedance.
20	IN_N	input	Line driver differential input (negative), 15 kΩ typical differential input impedance.
21	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-20-EP(4x4)
Category	Communication Interface Chip/UART/485/232
Pins	21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Quiescent supply current ATX4	IVDD	14.8	17.4	20	mA	ATX4	9
Quiescent supply current ATX3	IVDD	13.3	15.6	17.9	mA	ATX3	9
Quiescent supply current ATX2	IVDD	10.7	12.6	14.5	mA	ATX2	9
Quiescent supply current ATX1	IVDD	9.4	11	12.7	mA	ATX1	9
Quiescent supply current VTX4	IVDD	19.3	22.7	26.1	mA	VTX4	10
Quiescent supply current VTX3	IVDD	17.8	20.9	24	mA	VTX3	10
Quiescent supply current VTX2	IVDD	15.1	17.8	20.5	mA	VTX2	10
Quiescent supply current VTX1	IVDD	13.7	16.1	18.5	mA	VTX1	10
Quiescent supply current, power down	IVDD	0.4	0.6	0.8	mA	Power down state	10
Gain	AV	7.88	8.03	8.2	V/V		10
Gain flatness	AVF	-0.3		0.3	dB	f < Signal BW	10
Input impedance	RI	12	15	18	kΩ	Differential	10
Input middle voltage C0	VIM	1.4	1.5	1.6	V	C0	10
Input high voltage	VIH	2			V		10
Input low voltage	VIL			0.8	V		10
Input high current C0	IIH	15	50	85	µA	VIH = 3 V, C0	10
Input high current C1, C2	IIH	60	120	180	µA	VIH = 3 V, C1, C2	11
Input low current C0	IIL	-85	-50	-15	µA	VIL = 0 V, C0	11
Input low current C1, C2	IIL	-2	0	2	µA	VIL = 0 V, C1, C2	11
Supply voltage VDD with respect to VSS (abs max)	VDD	-0.3		16	V	VDD with respect to VSS	8
Control inputs with respect to VSS (abs max)		-0.3		4	V	Control inputs with respect to VSS	8
Junction temperature (abs max)	TJ	-40		150	°C		8
Supply voltage VDD/VDD_P/VDD_N	VDD	12.6	14	15.4	V		9
Ambient temperature	TA	-40	25	85	°C		9
Line impedance		80	100	150	Ω		9
Maximum device power dissipation, continuous				1.37	W	TA = 150 °C	8
Junction to ambient thermal resistance	θJA		47.5		°C/W	4-layer JEDEC PCB, 12 thermal vias, still air	8
Junction-to-board thermal resistance	θJB		25.8		°C/W		8
Junction-to-case bottom (exposed pad) thermal resistance	θJP		11.7		°C/W		8
Junction-to-top characterization parameter	θJC		30.8		°C/W		8
Supply power	PVDD		600		mW	PLine = 13 dBm	10
Output voltage	VOUT		10.5		Vpkd	Between OUT_P/N	10
Drive current	IOUT		240		mApk	Through OUT_P/N	10
Logic input impedance	Zin		25		kΩ		11

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		tin	and antimony-free materials. The leads possess a matte-tin plating, which is compatible with conventional board assembly processes or newer lead-free board assembly processes.	8

CAD (KiCad official)

Symbol: LE87271EQCT
Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
3D model: QFN-20-EP(4x4) (KiCad packages3D, STEP)
3D model files: le87271eqct-etched.step / le87271eqct-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); le87271eqct.step / le87271eqct.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (17 pp, sha256 aa10e9981fec82b6, retrieved 2026-10-30, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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LE87271EQCT

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3D Model

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