LD59150PURY

{
  "slug": "ld59150pury",
  "version": "0.1.0",
  "type": "component",
  "description": "STMicroelectronics Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, DFN-10(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "power management (pmic)",
    "ld59150pury",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
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    "README.md",
    "ld59150pury.kicad_sym",
    "ld59150pury.kicad_mod",
    "ld59150pury.glb",
    "ld59150pury.step",
    "ld59150pury.lbr",
    "docs/hero.png",
    "docs/ld59150pury-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "ld59150pury-hero.glb",
    "ld59150pury-hero.overlay.json"
  ],
  "component": {
    "mpn": "LD59150PURY",
    "manufacturer": "STMicroelectronics",
    "package": "DFN-10(3x3)",
    "pin_count": 11,
    "category": "Power Management (PMIC)",
    "subcategory": "Voltage Regulators - Linear, Low Drop Out (LDO) Regulators",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603155613577342976",
    "parts": {
      "symbol": "ld59150pury.kicad_sym",
      "footprint": "ld59150pury.kicad_mod",
      "model_3d": "ld59150pury-hero.glb",
      "model_3d_plain": "ld59150pury.glb",
      "model_3d_step": "ld59150pury-etched.step",
      "model_3d_step_plain": "ld59150pury.step",
      "lbr": "ld59150pury.lbr"
    },
    "distributor_links": {
      "lcsc": "C2969831",
      "digikey": "497-18285-2-ND",
      "mouser": "511-LD59150PURY"
    },
    "distributor_check": {
      "checked_at": "2026-10-10T22:04:59Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "497-18285-2-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "511-LD59150PURY",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VIN",
        "type": "power_in",
        "description": "Input pin of the LDO, with an operating input voltage range of 0.8 V to 5.5 V and an absolute maximum of -0.3 V to 6 V referred to GND."
      },
      {
        "number": "2",
        "name": "VIN",
        "type": "power_in",
        "description": "Input pin of the LDO (second VIN pin, bonded in parallel with pin 1), with an operating input voltage range of 0.8 V to 5.5 V and an absolute maximum of -0.3 V to 6 V referred to GND."
      },
      {
        "number": "3",
        "name": "PG",
        "type": "output",
        "description": "Open-drain Power Good flag that goes high-impedance when VOUT exceeds VIT + VHYS and is pulled low when VOUT falls below VIT (typ. 90% of VOUT); it needs an external pull-up to no more than 5.5 V, with typical capability up to 1 mA and a sink current rating of 0 to 1.5 mA."
      },
      {
        "number": "4",
        "name": "VBIAS",
        "type": "power_in",
        "description": "Bias supply pin with a specified range of 2.7 V to 5.5 V and an absolute maximum of -0.3 V to 6 V, which supplies the internal circuitry (typical IBIAS 0.88 to 1.5 mA)."
      },
      {
        "number": "5",
        "name": "EN",
        "type": "input",
        "description": "Enable logic input where low (VEN < 0.4 V) shuts the regulator down and high (VEN ≥ 1.1 V) activates it, with an absolute maximum of -0.3 V to 6 V, and it must not be left floating."
      },
      {
        "number": "6",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference pin to which all voltages are referred, and which must be connected to the exposed pad."
      },
      {
        "number": "7",
        "name": "SS",
        "type": "passive",
        "description": "Soft-start pin where an external capacitor CSS sets the output ramp time via tSS = (VREF × CSS) / ISS, with ISS = 0.44 µA typ. and an absolute maximum of -0.3 V to 6 V."
      },
      {
        "number": "8",
        "name": "FB",
        "type": "input",
        "description": "Feedback pin connected to the resistor divider so that VOUT = VREF (1 + R1/R2) with VREF = 0.8 V typ., with feedback pin current limited to ±1 µA."
      },
      {
        "number": "9",
        "name": "VOUT",
        "type": "power_out",
        "description": "Regulated output pin, adjustable from 0.8 V to 3.6 V, which requires a low-ESR output capacitor greater than 2.2 µF for stability."
      },
      {
        "number": "10",
        "name": "VOUT",
        "type": "power_out",
        "description": "Regulated output pin (second VOUT pin, bonded in parallel with pin 9), adjustable from 0.8 V to 3.6 V, which requires a low-ESR output capacitor greater than 2.2 µF for stability."
      },
      {
        "number": "11",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The datasheet names the exposed pad (must be connected to GND) but does not give it a pin number, so; The cover page header reads 'DFN6 (3x3)' while the features list, Figure 2 and Table 1 describe the ; Pin descriptions for VIN, VBIAS, EN and VOUT combine Table 1 with limits from the features list and ",
          "exposed pad 11 added from the footprint"
        ],
        "pages_sent": 22,
        "cost_usd": 0.057,
        "at": "2026-10-10T22:04:47"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603155613577342976",
        "pages": 22,
        "sha256": "fcfb83643350e4e1",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 11,
        "described": 11,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "ld59150pury.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          3.0,
          2.98,
          0.77
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "738e2eb45860c11759f8e4f44ab26932b7c15e4d5d6c8c9ac22ae866a3e38711",
        "checked": "2026-10-10",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ld59150pury-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "77fd86478ad8c7ddf151963ab0753e744924e0489b7bd01985ccb3c4b0fab41a",
        "checked": "2026-10-10",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}