component
LD59150PURY
Public Made by Adomby adom
STMicroelectronics Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, DFN-10(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLD59150PURY
STMicroelectronics · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DFN-10(3x3)
LD59150PURY from STMicroelectronics, in a DFN-10(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input pin of the LDO, with an operating input voltage range of 0.8 V to 5.5 V and an absolute maximum of -0.3 V to 6 V referred to GND. |
| 2 | VIN | power_in | Input pin of the LDO (second VIN pin, bonded in parallel with pin 1), with an operating input voltage range of 0.8 V to 5.5 V and an absolute maximum of -0.3 V to 6 V referred to GND. |
| 3 | PG | output | Open-drain Power Good flag that goes high-impedance when VOUT exceeds VIT + VHYS and is pulled low when VOUT falls below VIT (typ. 90% of VOUT); it needs an external pull-up to no more than 5.5 V, with typical capability up to 1 mA and a sink current rating of 0 to 1.5 mA. |
| 4 | VBIAS | power_in | Bias supply pin with a specified range of 2.7 V to 5.5 V and an absolute maximum of -0.3 V to 6 V, which supplies the internal circuitry (typical IBIAS 0.88 to 1.5 mA). |
| 5 | EN | input | Enable logic input where low (VEN < 0.4 V) shuts the regulator down and high (VEN ≥ 1.1 V) activates it, with an absolute maximum of -0.3 V to 6 V, and it must not be left floating. |
| 6 | GND | power_in | Ground reference pin to which all voltages are referred, and which must be connected to the exposed pad. |
| 7 | SS | passive | Soft-start pin where an external capacitor CSS sets the output ramp time via tSS = (VREF × CSS) / ISS, with ISS = 0.44 µA typ. and an absolute maximum of -0.3 V to 6 V. |
| 8 | FB | input | Feedback pin connected to the resistor divider so that VOUT = VREF (1 + R1/R2) with VREF = 0.8 V typ., with feedback pin current limited to ±1 µA. |
| 9 | VOUT | power_out | Regulated output pin, adjustable from 0.8 V to 3.6 V, which requires a low-ESR output capacitor greater than 2.2 µF for stability. |
| 10 | VOUT | power_out | Regulated output pin (second VOUT pin, bonded in parallel with pin 9), adjustable from 0.8 V to 3.6 V, which requires a low-ESR output capacitor greater than 2.2 µF for stability. |
| 11 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | DFN-10(3x3) |
| Category | Power Management (PMIC) |
| Pins | 11 |
CAD (KiCad official)
- Symbol:
LD59150PURY - Footprint:
Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm - 3D model: DFN-10(3x3) (KiCad packages3D, STEP)
- 3D model files:
ld59150pury-etched.step/ld59150pury-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ld59150pury.step/ld59150pury.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (22 pp, sha256
fcfb83643350e4e1, retrieved 2026-10-10, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).